![Paul Mackerras](/assets/img/avatar_default.png)
This fixes various issues in how we were handling the VSX registers that exist on POWER7 machines. First, we were running off the end of the current->thread.fpr[] array. Ultimately this was because the vcpu->arch.vsr[] array is sized to be able to store both the FP registers and the extra VSX registers (i.e. 64 entries), but PR KVM only uses it for the extra VSX registers (i.e. 32 entries). Secondly, calling load_up_vsx() from C code is a really bad idea, because it jumps to fast_exception_return at the end, rather than returning with a blr instruction. This was causing it to jump off to a random location with random register contents, since it was using the largely uninitialized stack frame created by kvmppc_load_up_vsx. In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx, since giveup_fpu and load_up_fpu handle the extra VSX registers as well as the standard FP registers on machines with VSX. Also, since VSX instructions can access the VMX registers and the FP registers as well as the extra VSX registers, we have to load up the FP and VMX registers before we can turn on the MSR_VSX bit for the guest. Conversely, if we save away any of the VSX or FP registers, we have to turn off MSR_VSX for the guest. To handle all this, it is more convenient for a single call to kvmppc_giveup_ext() to handle all the state saving that needs to be done, so we make it take a set of MSR bits rather than just one, and the switch statement becomes a series of if statements. Similarly kvmppc_handle_ext needs to be able to load up more than one set of registers. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
239 lines
6 KiB
ArmAsm
239 lines
6 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2009
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#include <asm/ppc_asm.h>
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#include <asm/kvm_asm.h>
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#include <asm/reg.h>
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#include <asm/mmu.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_PPC_BOOK3S_64
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#include <asm/exception-64s.h>
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#endif
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/*****************************************************************************
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* *
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* Real Mode handlers that need to be in low physical memory *
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* *
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****************************************************************************/
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#if defined(CONFIG_PPC_BOOK3S_64)
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#define FUNC(name) GLUE(.,name)
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.globl kvmppc_skip_interrupt
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kvmppc_skip_interrupt:
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/*
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* Here all GPRs are unchanged from when the interrupt happened
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* except for r13, which is saved in SPRG_SCRATCH0.
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*/
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mfspr r13, SPRN_SRR0
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addi r13, r13, 4
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mtspr SPRN_SRR0, r13
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GET_SCRATCH0(r13)
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rfid
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b .
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.globl kvmppc_skip_Hinterrupt
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kvmppc_skip_Hinterrupt:
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/*
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* Here all GPRs are unchanged from when the interrupt happened
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* except for r13, which is saved in SPRG_SCRATCH0.
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*/
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mfspr r13, SPRN_HSRR0
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addi r13, r13, 4
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mtspr SPRN_HSRR0, r13
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GET_SCRATCH0(r13)
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hrfid
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b .
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#elif defined(CONFIG_PPC_BOOK3S_32)
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#define FUNC(name) name
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.macro INTERRUPT_TRAMPOLINE intno
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.global kvmppc_trampoline_\intno
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kvmppc_trampoline_\intno:
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mtspr SPRN_SPRG_SCRATCH0, r13 /* Save r13 */
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/*
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* First thing to do is to find out if we're coming
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* from a KVM guest or a Linux process.
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*
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* To distinguish, we check a magic byte in the PACA/current
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*/
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mfspr r13, SPRN_SPRG_THREAD
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lwz r13, THREAD_KVM_SVCPU(r13)
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/* PPC32 can have a NULL pointer - let's check for that */
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mtspr SPRN_SPRG_SCRATCH1, r12 /* Save r12 */
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mfcr r12
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cmpwi r13, 0
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bne 1f
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2: mtcr r12
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mfspr r12, SPRN_SPRG_SCRATCH1
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mfspr r13, SPRN_SPRG_SCRATCH0 /* r13 = original r13 */
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b kvmppc_resume_\intno /* Get back original handler */
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1: tophys(r13, r13)
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stw r12, HSTATE_SCRATCH1(r13)
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mfspr r12, SPRN_SPRG_SCRATCH1
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stw r12, HSTATE_SCRATCH0(r13)
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lbz r12, HSTATE_IN_GUEST(r13)
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cmpwi r12, KVM_GUEST_MODE_NONE
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bne ..kvmppc_handler_hasmagic_\intno
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/* No KVM guest? Then jump back to the Linux handler! */
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lwz r12, HSTATE_SCRATCH1(r13)
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b 2b
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/* Now we know we're handling a KVM guest */
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..kvmppc_handler_hasmagic_\intno:
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/* Should we just skip the faulting instruction? */
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cmpwi r12, KVM_GUEST_MODE_SKIP
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beq kvmppc_handler_skip_ins
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/* Let's store which interrupt we're handling */
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li r12, \intno
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/* Jump into the SLB exit code that goes to the highmem handler */
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b kvmppc_handler_trampoline_exit
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.endm
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_SYSTEM_RESET
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_MACHINE_CHECK
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DATA_STORAGE
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_INST_STORAGE
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_EXTERNAL
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALIGNMENT
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_PROGRAM
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_FP_UNAVAIL
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_DECREMENTER
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_SYSCALL
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_TRACE
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_PERFMON
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INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALTIVEC
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/*
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* Bring us back to the faulting code, but skip the
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* faulting instruction.
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*
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* This is a generic exit path from the interrupt
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* trampolines above.
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*
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* Input Registers:
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*
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* R12 = free
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* R13 = Shadow VCPU (PACA)
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* HSTATE.SCRATCH0 = guest R12
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* HSTATE.SCRATCH1 = guest CR
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* SPRG_SCRATCH0 = guest R13
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*
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*/
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kvmppc_handler_skip_ins:
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/* Patch the IP to the next instruction */
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mfsrr0 r12
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addi r12, r12, 4
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mtsrr0 r12
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/* Clean up all state */
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lwz r12, HSTATE_SCRATCH1(r13)
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mtcr r12
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PPC_LL r12, HSTATE_SCRATCH0(r13)
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GET_SCRATCH0(r13)
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/* And get back into the code */
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RFI
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#endif
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/*
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* Call kvmppc_handler_trampoline_enter in real mode
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*
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* On entry, r4 contains the guest shadow MSR
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* MSR.EE has to be 0 when calling this function
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*/
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_GLOBAL(kvmppc_entry_trampoline)
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mfmsr r5
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LOAD_REG_ADDR(r7, kvmppc_handler_trampoline_enter)
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toreal(r7)
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li r6, MSR_IR | MSR_DR
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andc r6, r5, r6 /* Clear DR and IR in MSR value */
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/*
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* Set EE in HOST_MSR so that it's enabled when we get into our
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* C exit handler function
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*/
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ori r5, r5, MSR_EE
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mtsrr0 r7
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mtsrr1 r6
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RFI
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#if defined(CONFIG_PPC_BOOK3S_32)
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#define STACK_LR INT_FRAME_SIZE+4
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/* load_up_xxx have to run with MSR_DR=0 on Book3S_32 */
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#define MSR_EXT_START \
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PPC_STL r20, _NIP(r1); \
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mfmsr r20; \
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LOAD_REG_IMMEDIATE(r3, MSR_DR|MSR_EE); \
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andc r3,r20,r3; /* Disable DR,EE */ \
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mtmsr r3; \
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sync
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#define MSR_EXT_END \
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mtmsr r20; /* Enable DR,EE */ \
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sync; \
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PPC_LL r20, _NIP(r1)
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#elif defined(CONFIG_PPC_BOOK3S_64)
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#define STACK_LR _LINK
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#define MSR_EXT_START
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#define MSR_EXT_END
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#endif
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/*
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* Activate current's external feature (FPU/Altivec/VSX)
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*/
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#define define_load_up(what) \
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\
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_GLOBAL(kvmppc_load_up_ ## what); \
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PPC_STLU r1, -INT_FRAME_SIZE(r1); \
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mflr r3; \
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PPC_STL r3, STACK_LR(r1); \
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MSR_EXT_START; \
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\
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bl FUNC(load_up_ ## what); \
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\
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MSR_EXT_END; \
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PPC_LL r3, STACK_LR(r1); \
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mtlr r3; \
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addi r1, r1, INT_FRAME_SIZE; \
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blr
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define_load_up(fpu)
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#ifdef CONFIG_ALTIVEC
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define_load_up(altivec)
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#endif
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#include "book3s_segment.S"
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