![Ben Widawsky](/assets/img/avatar_default.png)
When I refactored the code initially, I forgot that gen2 uses a
different bar for the CPU mappable aperture. The agp-less code knows
nothing of generations less than 5, so we have to expand the gtt_probe
function to include the mappable base and end.
It was originally broken by me:
commit baa09f5fd8
Author: Ben Widawsky <ben@bwidawsk.net>
Date: Thu Jan 24 13:49:57 2013 -0800
drm/i915: Add probe and remove to the gtt ops
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
850 lines
23 KiB
C
850 lines
23 KiB
C
/*
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* Copyright © 2010 Daniel Vetter
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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typedef uint32_t gtt_pte_t;
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/* PPGTT stuff */
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#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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#define GEN6_PDE_VALID (1 << 0)
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/* gen6+ has bit 11-4 for physical addr bit 39-32 */
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#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PTE_VALID (1 << 0)
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#define GEN6_PTE_UNCACHED (1 << 1)
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#define HSW_PTE_UNCACHED (0)
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
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#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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static inline gtt_pte_t gen6_pte_encode(struct drm_device *dev,
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dma_addr_t addr,
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enum i915_cache_level level)
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{
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gtt_pte_t pte = GEN6_PTE_VALID;
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pte |= GEN6_PTE_ADDR_ENCODE(addr);
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switch (level) {
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case I915_CACHE_LLC_MLC:
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/* Haswell doesn't set L3 this way */
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if (IS_HASWELL(dev))
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pte |= GEN6_PTE_CACHE_LLC;
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else
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pte |= GEN6_PTE_CACHE_LLC_MLC;
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break;
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case I915_CACHE_LLC:
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pte |= GEN6_PTE_CACHE_LLC;
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break;
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case I915_CACHE_NONE:
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if (IS_HASWELL(dev))
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pte |= HSW_PTE_UNCACHED;
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else
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pte |= GEN6_PTE_UNCACHED;
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break;
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default:
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BUG();
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}
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return pte;
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}
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/* PPGTT support for Sandybdrige/Gen6 and later */
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static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
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unsigned first_entry,
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unsigned num_entries)
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{
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gtt_pte_t *pt_vaddr;
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gtt_pte_t scratch_pte;
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unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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unsigned last_pte, i;
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scratch_pte = gen6_pte_encode(ppgtt->dev,
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ppgtt->scratch_page_dma_addr,
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I915_CACHE_LLC);
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while (num_entries) {
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last_pte = first_pte + num_entries;
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if (last_pte > I915_PPGTT_PT_ENTRIES)
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last_pte = I915_PPGTT_PT_ENTRIES;
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pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
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for (i = first_pte; i < last_pte; i++)
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pt_vaddr[i] = scratch_pte;
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kunmap_atomic(pt_vaddr);
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num_entries -= last_pte - first_pte;
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first_pte = 0;
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act_pd++;
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}
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}
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static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
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struct sg_table *pages,
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unsigned first_entry,
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enum i915_cache_level cache_level)
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{
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gtt_pte_t *pt_vaddr;
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unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
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unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
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unsigned i, j, m, segment_len;
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dma_addr_t page_addr;
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struct scatterlist *sg;
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/* init sg walking */
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sg = pages->sgl;
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i = 0;
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segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
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m = 0;
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while (i < pages->nents) {
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pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
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for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
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page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
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pt_vaddr[j] = gen6_pte_encode(ppgtt->dev, page_addr,
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cache_level);
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/* grab the next page */
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if (++m == segment_len) {
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if (++i == pages->nents)
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break;
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sg = sg_next(sg);
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segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
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m = 0;
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}
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}
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kunmap_atomic(pt_vaddr);
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first_pte = 0;
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act_pd++;
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}
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}
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static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
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{
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int i;
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if (ppgtt->pt_dma_addr) {
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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pci_unmap_page(ppgtt->dev->pdev,
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ppgtt->pt_dma_addr[i],
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4096, PCI_DMA_BIDIRECTIONAL);
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}
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kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++)
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__free_page(ppgtt->pt_pages[i]);
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kfree(ppgtt->pt_pages);
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kfree(ppgtt);
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}
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static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
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{
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struct drm_device *dev = ppgtt->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned first_pd_entry_in_global_pt;
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int i;
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int ret = -ENOMEM;
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/* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
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* entries. For aliasing ppgtt support we just steal them at the end for
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* now. */
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first_pd_entry_in_global_pt =
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gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
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ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
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ppgtt->clear_range = gen6_ppgtt_clear_range;
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ppgtt->insert_entries = gen6_ppgtt_insert_entries;
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ppgtt->cleanup = gen6_ppgtt_cleanup;
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ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_pages)
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return -ENOMEM;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
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if (!ppgtt->pt_pages[i])
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goto err_pt_alloc;
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}
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ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
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GFP_KERNEL);
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if (!ppgtt->pt_dma_addr)
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goto err_pt_alloc;
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
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ret = -EIO;
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goto err_pd_pin;
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}
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ppgtt->pt_dma_addr[i] = pt_addr;
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}
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ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
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ppgtt->clear_range(ppgtt, 0,
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ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
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ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t);
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return 0;
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err_pd_pin:
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if (ppgtt->pt_dma_addr) {
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for (i--; i >= 0; i--)
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pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
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4096, PCI_DMA_BIDIRECTIONAL);
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}
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err_pt_alloc:
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kfree(ppgtt->pt_dma_addr);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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if (ppgtt->pt_pages[i])
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__free_page(ppgtt->pt_pages[i]);
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}
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kfree(ppgtt->pt_pages);
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return ret;
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}
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static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt;
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int ret;
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ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
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if (!ppgtt)
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return -ENOMEM;
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ppgtt->dev = dev;
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ret = gen6_ppgtt_init(ppgtt);
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if (ret)
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kfree(ppgtt);
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else
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dev_priv->mm.aliasing_ppgtt = ppgtt;
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return ret;
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}
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void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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if (!ppgtt)
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return;
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ppgtt->cleanup(ppgtt);
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}
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void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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{
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ppgtt->insert_entries(ppgtt, obj->pages,
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obj->gtt_space->start >> PAGE_SHIFT,
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cache_level);
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}
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void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_object *obj)
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{
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ppgtt->clear_range(ppgtt,
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obj->gtt_space->start >> PAGE_SHIFT,
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obj->base.size >> PAGE_SHIFT);
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}
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void i915_gem_init_ppgtt(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t pd_offset;
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struct intel_ring_buffer *ring;
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struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
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gtt_pte_t __iomem *pd_addr;
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uint32_t pd_entry;
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int i;
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if (!dev_priv->mm.aliasing_ppgtt)
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return;
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pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t);
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for (i = 0; i < ppgtt->num_pd_entries; i++) {
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dma_addr_t pt_addr;
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pt_addr = ppgtt->pt_dma_addr[i];
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pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
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pd_entry |= GEN6_PDE_VALID;
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writel(pd_entry, pd_addr + i);
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}
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readl(pd_addr);
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pd_offset = ppgtt->pd_offset;
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pd_offset /= 64; /* in cachelines, */
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pd_offset <<= 16;
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if (INTEL_INFO(dev)->gen == 6) {
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uint32_t ecochk, gab_ctl, ecobits;
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ecobits = I915_READ(GAC_ECO_BITS);
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I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
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gab_ctl = I915_READ(GAB_CTL);
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I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
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ecochk = I915_READ(GAM_ECOCHK);
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I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
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ECOCHK_PPGTT_CACHE64B);
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I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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} else if (INTEL_INFO(dev)->gen >= 7) {
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I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
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/* GFX_MODE is per-ring on gen7+ */
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}
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for_each_ring(ring, dev_priv, i) {
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if (INTEL_INFO(dev)->gen >= 7)
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I915_WRITE(RING_MODE_GEN7(ring),
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_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
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I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
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I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
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}
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}
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extern int intel_iommu_gfx_mapped;
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/* Certain Gen5 chipsets require require idling the GPU before
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* unmapping anything from the GTT when VT-d is enabled.
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*/
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static inline bool needs_idle_maps(struct drm_device *dev)
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{
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#ifdef CONFIG_INTEL_IOMMU
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/* Query intel_iommu to see if we need the workaround. Presumably that
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* was loaded first.
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*/
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if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
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return true;
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#endif
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return false;
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}
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static bool do_idling(struct drm_i915_private *dev_priv)
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{
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bool ret = dev_priv->mm.interruptible;
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if (unlikely(dev_priv->gtt.do_idle_maps)) {
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dev_priv->mm.interruptible = false;
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if (i915_gpu_idle(dev_priv->dev)) {
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DRM_ERROR("Couldn't idle GPU\n");
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/* Wait a bit, in hopes it avoids the hang */
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udelay(10);
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}
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}
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return ret;
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}
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static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
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{
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if (unlikely(dev_priv->gtt.do_idle_maps))
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dev_priv->mm.interruptible = interruptible;
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}
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void i915_gem_restore_gtt_mappings(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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/* First fill our portion of the GTT with scratch pages */
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dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
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dev_priv->gtt.total / PAGE_SIZE);
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list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
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i915_gem_clflush_object(obj);
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i915_gem_gtt_bind_object(obj, obj->cache_level);
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}
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i915_gem_chipset_flush(dev);
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}
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int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
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{
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if (obj->has_dma_mapping)
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return 0;
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if (!dma_map_sg(&obj->base.dev->pdev->dev,
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obj->pages->sgl, obj->pages->nents,
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PCI_DMA_BIDIRECTIONAL))
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return -ENOSPC;
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return 0;
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}
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/*
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* Binds an object into the global gtt with the specified cache level. The object
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* will be accessible to the GPU via commands whose operands reference offsets
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* within the global GTT as well as accessible by the GPU through the GMADR
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* mapped BAR (dev_priv->mm.gtt->gtt).
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*/
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static void gen6_ggtt_insert_entries(struct drm_device *dev,
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struct sg_table *st,
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unsigned int first_entry,
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enum i915_cache_level level)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct scatterlist *sg = st->sgl;
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gtt_pte_t __iomem *gtt_entries =
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(gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
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int unused, i = 0;
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unsigned int len, m = 0;
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dma_addr_t addr;
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for_each_sg(st->sgl, sg, st->nents, unused) {
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len = sg_dma_len(sg) >> PAGE_SHIFT;
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for (m = 0; m < len; m++) {
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addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
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iowrite32(gen6_pte_encode(dev, addr, level),
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>t_entries[i]);
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i++;
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}
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}
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/* XXX: This serves as a posting read to make sure that the PTE has
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* actually been updated. There is some concern that even though
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* registers and PTEs are within the same BAR that they are potentially
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* of NUMA access patterns. Therefore, even with the way we assume
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* hardware should work, we must keep this posting read for paranoia.
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*/
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if (i != 0)
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WARN_ON(readl(>t_entries[i-1])
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!= gen6_pte_encode(dev, addr, level));
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/* This next bit makes the above posting read even more important. We
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* want to flush the TLBs only after we're certain all the PTE updates
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* have finished.
|
|
*/
|
|
I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
|
|
POSTING_READ(GFX_FLSH_CNTL_GEN6);
|
|
}
|
|
|
|
static void gen6_ggtt_clear_range(struct drm_device *dev,
|
|
unsigned int first_entry,
|
|
unsigned int num_entries)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
gtt_pte_t scratch_pte;
|
|
gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
|
|
const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
|
|
int i;
|
|
|
|
if (WARN(num_entries > max_entries,
|
|
"First entry = %d; Num entries = %d (max=%d)\n",
|
|
first_entry, num_entries, max_entries))
|
|
num_entries = max_entries;
|
|
|
|
scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
|
|
I915_CACHE_LLC);
|
|
for (i = 0; i < num_entries; i++)
|
|
iowrite32(scratch_pte, >t_base[i]);
|
|
readl(gtt_base);
|
|
}
|
|
|
|
|
|
static void i915_ggtt_insert_entries(struct drm_device *dev,
|
|
struct sg_table *st,
|
|
unsigned int pg_start,
|
|
enum i915_cache_level cache_level)
|
|
{
|
|
unsigned int flags = (cache_level == I915_CACHE_NONE) ?
|
|
AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
|
|
|
|
intel_gtt_insert_sg_entries(st, pg_start, flags);
|
|
|
|
}
|
|
|
|
static void i915_ggtt_clear_range(struct drm_device *dev,
|
|
unsigned int first_entry,
|
|
unsigned int num_entries)
|
|
{
|
|
intel_gtt_clear_range(first_entry, num_entries);
|
|
}
|
|
|
|
|
|
void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
|
|
enum i915_cache_level cache_level)
|
|
{
|
|
struct drm_device *dev = obj->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
|
|
obj->gtt_space->start >> PAGE_SHIFT,
|
|
cache_level);
|
|
|
|
obj->has_global_gtt_mapping = 1;
|
|
}
|
|
|
|
void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_device *dev = obj->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
dev_priv->gtt.gtt_clear_range(obj->base.dev,
|
|
obj->gtt_space->start >> PAGE_SHIFT,
|
|
obj->base.size >> PAGE_SHIFT);
|
|
|
|
obj->has_global_gtt_mapping = 0;
|
|
}
|
|
|
|
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_device *dev = obj->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
bool interruptible;
|
|
|
|
interruptible = do_idling(dev_priv);
|
|
|
|
if (!obj->has_dma_mapping)
|
|
dma_unmap_sg(&dev->pdev->dev,
|
|
obj->pages->sgl, obj->pages->nents,
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
|
|
undo_idling(dev_priv, interruptible);
|
|
}
|
|
|
|
static void i915_gtt_color_adjust(struct drm_mm_node *node,
|
|
unsigned long color,
|
|
unsigned long *start,
|
|
unsigned long *end)
|
|
{
|
|
if (node->color != color)
|
|
*start += 4096;
|
|
|
|
if (!list_empty(&node->node_list)) {
|
|
node = list_entry(node->node_list.next,
|
|
struct drm_mm_node,
|
|
node_list);
|
|
if (node->allocated && node->color != color)
|
|
*end -= 4096;
|
|
}
|
|
}
|
|
void i915_gem_setup_global_gtt(struct drm_device *dev,
|
|
unsigned long start,
|
|
unsigned long mappable_end,
|
|
unsigned long end)
|
|
{
|
|
/* Let GEM Manage all of the aperture.
|
|
*
|
|
* However, leave one page at the end still bound to the scratch page.
|
|
* There are a number of places where the hardware apparently prefetches
|
|
* past the end of the object, and we've seen multiple hangs with the
|
|
* GPU head pointer stuck in a batchbuffer bound at the last page of the
|
|
* aperture. One page should be enough to keep any prefetching inside
|
|
* of the aperture.
|
|
*/
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct drm_mm_node *entry;
|
|
struct drm_i915_gem_object *obj;
|
|
unsigned long hole_start, hole_end;
|
|
|
|
BUG_ON(mappable_end > end);
|
|
|
|
/* Subtract the guard page ... */
|
|
drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
|
|
if (!HAS_LLC(dev))
|
|
dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
|
|
|
|
/* Mark any preallocated objects as occupied */
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
|
|
DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
|
|
obj->gtt_offset, obj->base.size);
|
|
|
|
BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
|
|
obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
|
|
obj->gtt_offset,
|
|
obj->base.size,
|
|
false);
|
|
obj->has_global_gtt_mapping = 1;
|
|
}
|
|
|
|
dev_priv->gtt.start = start;
|
|
dev_priv->gtt.total = end - start;
|
|
|
|
/* Clear any non-preallocated blocks */
|
|
drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
|
|
hole_start, hole_end) {
|
|
DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
|
|
hole_start, hole_end);
|
|
dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
|
|
(hole_end-hole_start) / PAGE_SIZE);
|
|
}
|
|
|
|
/* And finally clear the reserved guard page */
|
|
dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
|
|
}
|
|
|
|
static bool
|
|
intel_enable_ppgtt(struct drm_device *dev)
|
|
{
|
|
if (i915_enable_ppgtt >= 0)
|
|
return i915_enable_ppgtt;
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
/* Disable ppgtt on SNB if VT-d is on. */
|
|
if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
|
|
return false;
|
|
#endif
|
|
|
|
return true;
|
|
}
|
|
|
|
void i915_gem_init_global_gtt(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
unsigned long gtt_size, mappable_size;
|
|
|
|
gtt_size = dev_priv->gtt.total;
|
|
mappable_size = dev_priv->gtt.mappable_end;
|
|
|
|
if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
|
|
int ret;
|
|
/* PPGTT pdes are stolen from global gtt ptes, so shrink the
|
|
* aperture accordingly when using aliasing ppgtt. */
|
|
gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
|
|
|
|
i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
|
|
|
|
ret = i915_gem_init_aliasing_ppgtt(dev);
|
|
if (!ret)
|
|
return;
|
|
|
|
DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
|
|
drm_mm_takedown(&dev_priv->mm.gtt_space);
|
|
gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
|
|
}
|
|
i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
|
|
}
|
|
|
|
static int setup_scratch_page(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct page *page;
|
|
dma_addr_t dma_addr;
|
|
|
|
page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
|
|
if (page == NULL)
|
|
return -ENOMEM;
|
|
get_page(page);
|
|
set_pages_uc(page, 1);
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
if (pci_dma_mapping_error(dev->pdev, dma_addr))
|
|
return -EINVAL;
|
|
#else
|
|
dma_addr = page_to_phys(page);
|
|
#endif
|
|
dev_priv->gtt.scratch_page = page;
|
|
dev_priv->gtt.scratch_page_dma = dma_addr;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void teardown_scratch_page(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
set_pages_wb(dev_priv->gtt.scratch_page, 1);
|
|
pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
put_page(dev_priv->gtt.scratch_page);
|
|
__free_page(dev_priv->gtt.scratch_page);
|
|
}
|
|
|
|
static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
|
|
{
|
|
snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
|
|
snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
|
|
return snb_gmch_ctl << 20;
|
|
}
|
|
|
|
static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
|
|
{
|
|
snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
|
|
snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
|
|
return snb_gmch_ctl << 25; /* 32 MB units */
|
|
}
|
|
|
|
static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
|
|
{
|
|
static const int stolen_decoder[] = {
|
|
0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
|
|
snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
|
|
snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
|
|
return stolen_decoder[snb_gmch_ctl] << 20;
|
|
}
|
|
|
|
static int gen6_gmch_probe(struct drm_device *dev,
|
|
size_t *gtt_total,
|
|
size_t *stolen,
|
|
phys_addr_t *mappable_base,
|
|
unsigned long *mappable_end)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
phys_addr_t gtt_bus_addr;
|
|
unsigned int gtt_size;
|
|
u16 snb_gmch_ctl;
|
|
int ret;
|
|
|
|
*mappable_base = pci_resource_start(dev->pdev, 2);
|
|
*mappable_end = pci_resource_len(dev->pdev, 2);
|
|
|
|
/* 64/512MB is the current min/max we actually know of, but this is just
|
|
* a coarse sanity check.
|
|
*/
|
|
if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
|
|
DRM_ERROR("Unknown GMADR size (%lx)\n",
|
|
dev_priv->gtt.mappable_end);
|
|
return -ENXIO;
|
|
}
|
|
|
|
if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
|
|
pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
|
|
pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
|
|
gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
|
|
|
|
if (IS_GEN7(dev))
|
|
*stolen = gen7_get_stolen_size(snb_gmch_ctl);
|
|
else
|
|
*stolen = gen6_get_stolen_size(snb_gmch_ctl);
|
|
|
|
*gtt_total = (gtt_size / sizeof(gtt_pte_t)) << PAGE_SHIFT;
|
|
|
|
/* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
|
|
gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);
|
|
dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
|
|
if (!dev_priv->gtt.gsm) {
|
|
DRM_ERROR("Failed to map the gtt page table\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = setup_scratch_page(dev);
|
|
if (ret)
|
|
DRM_ERROR("Scratch setup failed\n");
|
|
|
|
dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
|
|
dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void gen6_gmch_remove(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
iounmap(dev_priv->gtt.gsm);
|
|
teardown_scratch_page(dev_priv->dev);
|
|
}
|
|
|
|
static int i915_gmch_probe(struct drm_device *dev,
|
|
size_t *gtt_total,
|
|
size_t *stolen,
|
|
phys_addr_t *mappable_base,
|
|
unsigned long *mappable_end)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int ret;
|
|
|
|
ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
|
|
if (!ret) {
|
|
DRM_ERROR("failed to set up gmch\n");
|
|
return -EIO;
|
|
}
|
|
|
|
intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
|
|
|
|
dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
|
|
dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
|
|
dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void i915_gmch_remove(struct drm_device *dev)
|
|
{
|
|
intel_gmch_remove();
|
|
}
|
|
|
|
int i915_gem_gtt_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct i915_gtt *gtt = &dev_priv->gtt;
|
|
unsigned long gtt_size;
|
|
int ret;
|
|
|
|
if (INTEL_INFO(dev)->gen <= 5) {
|
|
dev_priv->gtt.gtt_probe = i915_gmch_probe;
|
|
dev_priv->gtt.gtt_remove = i915_gmch_remove;
|
|
} else {
|
|
dev_priv->gtt.gtt_probe = gen6_gmch_probe;
|
|
dev_priv->gtt.gtt_remove = gen6_gmch_remove;
|
|
}
|
|
|
|
ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
|
|
&dev_priv->gtt.stolen_size,
|
|
>t->mappable_base,
|
|
>t->mappable_end);
|
|
if (ret)
|
|
return ret;
|
|
|
|
gtt_size = (dev_priv->gtt.total >> PAGE_SHIFT) * sizeof(gtt_pte_t);
|
|
|
|
/* GMADR is the PCI mmio aperture into the global GTT. */
|
|
DRM_INFO("Memory usable by graphics device = %zdM\n",
|
|
dev_priv->gtt.total >> 20);
|
|
DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
|
|
dev_priv->gtt.mappable_end >> 20);
|
|
DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
|
|
dev_priv->gtt.stolen_size >> 20);
|
|
|
|
return 0;
|
|
}
|