![Jan-Bernd Themann](/assets/img/avatar_default.png)
Hi Jeff, I fixed the __iomem issue and tested the driver with sparse. Looks good so far. Thanks for your effort. Jan-Bernd Themann Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com> drivers/net/Kconfig | 9 drivers/net/Makefile | 1 drivers/net/ehea/Makefile | 6 drivers/net/ehea/ehea.h | 447 ++++++ drivers/net/ehea/ehea_ethtool.c | 294 ++++ drivers/net/ehea/ehea_hcall.h | 51 drivers/net/ehea/ehea_hw.h | 287 ++++ drivers/net/ehea/ehea_main.c | 2654 ++++++++++++++++++++++++++++++++++++++++ drivers/net/ehea/ehea_phyp.c | 705 ++++++++++ drivers/net/ehea/ehea_phyp.h | 455 ++++++ drivers/net/ehea/ehea_qmr.c | 582 ++++++++ drivers/net/ehea/ehea_qmr.h | 358 +++++ 12 files changed, 5849 insertions(+) Signed-off-by: Jeff Garzik <jeff@garzik.org>
706 lines
23 KiB
C
706 lines
23 KiB
C
/*
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* linux/drivers/net/ehea/ehea_phyp.c
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*
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* eHEA ethernet device driver for IBM eServer System p
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*
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* (C) Copyright IBM Corp. 2006
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*
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* Authors:
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* Christoph Raisch <raisch@de.ibm.com>
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* Jan-Bernd Themann <themann@de.ibm.com>
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* Thomas Klein <tklein@de.ibm.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "ehea_phyp.h"
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static inline u16 get_order_of_qentries(u16 queue_entries)
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{
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u8 ld = 1; /* logarithmus dualis */
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while (((1U << ld) - 1) < queue_entries)
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ld++;
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return ld - 1;
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}
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/* Defines for H_CALL H_ALLOC_RESOURCE */
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#define H_ALL_RES_TYPE_QP 1
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#define H_ALL_RES_TYPE_CQ 2
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#define H_ALL_RES_TYPE_EQ 3
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#define H_ALL_RES_TYPE_MR 5
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#define H_ALL_RES_TYPE_MW 6
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static long ehea_hcall_9arg_9ret(unsigned long opcode,
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unsigned long arg1, unsigned long arg2,
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unsigned long arg3, unsigned long arg4,
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unsigned long arg5, unsigned long arg6,
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unsigned long arg7, unsigned long arg8,
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unsigned long arg9, unsigned long *out1,
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unsigned long *out2,unsigned long *out3,
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unsigned long *out4,unsigned long *out5,
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unsigned long *out6,unsigned long *out7,
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unsigned long *out8,unsigned long *out9)
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{
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long hret;
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int i, sleep_msecs;
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for (i = 0; i < 5; i++) {
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hret = plpar_hcall_9arg_9ret(opcode,arg1, arg2, arg3, arg4,
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arg5, arg6, arg7, arg8, arg9, out1,
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out2, out3, out4, out5, out6, out7,
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out8, out9);
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if (H_IS_LONG_BUSY(hret)) {
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sleep_msecs = get_longbusy_msecs(hret);
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msleep_interruptible(sleep_msecs);
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continue;
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}
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if (hret < H_SUCCESS)
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ehea_error("op=%lx hret=%lx "
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"i1=%lx i2=%lx i3=%lx i4=%lx i5=%lx i6=%lx "
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"i7=%lx i8=%lx i9=%lx "
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"o1=%lx o2=%lx o3=%lx o4=%lx o5=%lx o6=%lx "
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"o7=%lx o8=%lx o9=%lx",
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opcode, hret, arg1, arg2, arg3, arg4, arg5,
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arg6, arg7, arg8, arg9, *out1, *out2, *out3,
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*out4, *out5, *out6, *out7, *out8, *out9);
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return hret;
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}
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return H_BUSY;
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}
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u64 ehea_h_query_ehea_qp(const u64 adapter_handle, const u8 qp_category,
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const u64 qp_handle, const u64 sel_mask, void *cb_addr)
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{
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u64 dummy;
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if ((((u64)cb_addr) & (PAGE_SIZE - 1)) != 0) {
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ehea_error("not on pageboundary");
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return H_PARAMETER;
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}
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return ehea_hcall_9arg_9ret(H_QUERY_HEA_QP,
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adapter_handle, /* R4 */
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qp_category, /* R5 */
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qp_handle, /* R6 */
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sel_mask, /* R7 */
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virt_to_abs(cb_addr), /* R8 */
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0, 0, 0, 0, /* R9-R12 */
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&dummy, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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}
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/* input param R5 */
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#define H_ALL_RES_QP_EQPO EHEA_BMASK_IBM(9, 11)
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#define H_ALL_RES_QP_QPP EHEA_BMASK_IBM(12, 12)
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#define H_ALL_RES_QP_RQR EHEA_BMASK_IBM(13, 15)
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#define H_ALL_RES_QP_EQEG EHEA_BMASK_IBM(16, 16)
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#define H_ALL_RES_QP_LL_QP EHEA_BMASK_IBM(17, 17)
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#define H_ALL_RES_QP_DMA128 EHEA_BMASK_IBM(19, 19)
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#define H_ALL_RES_QP_HSM EHEA_BMASK_IBM(20, 21)
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#define H_ALL_RES_QP_SIGT EHEA_BMASK_IBM(22, 23)
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#define H_ALL_RES_QP_TENURE EHEA_BMASK_IBM(48, 55)
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#define H_ALL_RES_QP_RES_TYP EHEA_BMASK_IBM(56, 63)
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/* input param R9 */
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#define H_ALL_RES_QP_TOKEN EHEA_BMASK_IBM(0, 31)
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#define H_ALL_RES_QP_PD EHEA_BMASK_IBM(32,63)
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/* input param R10 */
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#define H_ALL_RES_QP_MAX_SWQE EHEA_BMASK_IBM(4, 7)
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#define H_ALL_RES_QP_MAX_R1WQE EHEA_BMASK_IBM(12, 15)
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#define H_ALL_RES_QP_MAX_R2WQE EHEA_BMASK_IBM(20, 23)
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#define H_ALL_RES_QP_MAX_R3WQE EHEA_BMASK_IBM(28, 31)
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/* Max Send Scatter Gather Elements */
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#define H_ALL_RES_QP_MAX_SSGE EHEA_BMASK_IBM(37, 39)
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#define H_ALL_RES_QP_MAX_R1SGE EHEA_BMASK_IBM(45, 47)
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/* Max Receive SG Elements RQ1 */
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#define H_ALL_RES_QP_MAX_R2SGE EHEA_BMASK_IBM(53, 55)
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#define H_ALL_RES_QP_MAX_R3SGE EHEA_BMASK_IBM(61, 63)
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/* input param R11 */
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#define H_ALL_RES_QP_SWQE_IDL EHEA_BMASK_IBM(0, 7)
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/* max swqe immediate data length */
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#define H_ALL_RES_QP_PORT_NUM EHEA_BMASK_IBM(48, 63)
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/* input param R12 */
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#define H_ALL_RES_QP_TH_RQ2 EHEA_BMASK_IBM(0, 15)
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/* Threshold RQ2 */
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#define H_ALL_RES_QP_TH_RQ3 EHEA_BMASK_IBM(16, 31)
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/* Threshold RQ3 */
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/* output param R6 */
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#define H_ALL_RES_QP_ACT_SWQE EHEA_BMASK_IBM(0, 15)
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#define H_ALL_RES_QP_ACT_R1WQE EHEA_BMASK_IBM(16, 31)
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#define H_ALL_RES_QP_ACT_R2WQE EHEA_BMASK_IBM(32, 47)
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#define H_ALL_RES_QP_ACT_R3WQE EHEA_BMASK_IBM(48, 63)
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/* output param, R7 */
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#define H_ALL_RES_QP_ACT_SSGE EHEA_BMASK_IBM(0, 7)
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#define H_ALL_RES_QP_ACT_R1SGE EHEA_BMASK_IBM(8, 15)
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#define H_ALL_RES_QP_ACT_R2SGE EHEA_BMASK_IBM(16, 23)
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#define H_ALL_RES_QP_ACT_R3SGE EHEA_BMASK_IBM(24, 31)
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#define H_ALL_RES_QP_ACT_SWQE_IDL EHEA_BMASK_IBM(32, 39)
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/* output param R8,R9 */
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#define H_ALL_RES_QP_SIZE_SQ EHEA_BMASK_IBM(0, 31)
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#define H_ALL_RES_QP_SIZE_RQ1 EHEA_BMASK_IBM(32, 63)
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#define H_ALL_RES_QP_SIZE_RQ2 EHEA_BMASK_IBM(0, 31)
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#define H_ALL_RES_QP_SIZE_RQ3 EHEA_BMASK_IBM(32, 63)
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/* output param R11,R12 */
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#define H_ALL_RES_QP_LIOBN_SQ EHEA_BMASK_IBM(0, 31)
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#define H_ALL_RES_QP_LIOBN_RQ1 EHEA_BMASK_IBM(32, 63)
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#define H_ALL_RES_QP_LIOBN_RQ2 EHEA_BMASK_IBM(0, 31)
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#define H_ALL_RES_QP_LIOBN_RQ3 EHEA_BMASK_IBM(32, 63)
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u64 ehea_h_alloc_resource_qp(const u64 adapter_handle,
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struct ehea_qp_init_attr *init_attr, const u32 pd,
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u64 *qp_handle, struct h_epas *h_epas)
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{
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u64 hret;
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u64 allocate_controls =
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EHEA_BMASK_SET(H_ALL_RES_QP_EQPO, init_attr->low_lat_rq1 ? 1 : 0)
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| EHEA_BMASK_SET(H_ALL_RES_QP_QPP, 0)
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| EHEA_BMASK_SET(H_ALL_RES_QP_RQR, 6) /* rq1 & rq2 & rq3 */
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| EHEA_BMASK_SET(H_ALL_RES_QP_EQEG, 0) /* EQE gen. disabled */
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| EHEA_BMASK_SET(H_ALL_RES_QP_LL_QP, init_attr->low_lat_rq1)
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| EHEA_BMASK_SET(H_ALL_RES_QP_DMA128, 0)
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| EHEA_BMASK_SET(H_ALL_RES_QP_HSM, 0)
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| EHEA_BMASK_SET(H_ALL_RES_QP_SIGT, init_attr->signalingtype)
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| EHEA_BMASK_SET(H_ALL_RES_QP_RES_TYP, H_ALL_RES_TYPE_QP);
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u64 r9_reg = EHEA_BMASK_SET(H_ALL_RES_QP_PD, pd)
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| EHEA_BMASK_SET(H_ALL_RES_QP_TOKEN, init_attr->qp_token);
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u64 max_r10_reg =
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EHEA_BMASK_SET(H_ALL_RES_QP_MAX_SWQE,
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get_order_of_qentries(init_attr->max_nr_send_wqes))
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| EHEA_BMASK_SET(H_ALL_RES_QP_MAX_R1WQE,
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get_order_of_qentries(init_attr->max_nr_rwqes_rq1))
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| EHEA_BMASK_SET(H_ALL_RES_QP_MAX_R2WQE,
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get_order_of_qentries(init_attr->max_nr_rwqes_rq2))
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| EHEA_BMASK_SET(H_ALL_RES_QP_MAX_R3WQE,
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get_order_of_qentries(init_attr->max_nr_rwqes_rq3))
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| EHEA_BMASK_SET(H_ALL_RES_QP_MAX_SSGE, init_attr->wqe_size_enc_sq)
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| EHEA_BMASK_SET(H_ALL_RES_QP_MAX_R1SGE,
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init_attr->wqe_size_enc_rq1)
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| EHEA_BMASK_SET(H_ALL_RES_QP_MAX_R2SGE,
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init_attr->wqe_size_enc_rq2)
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| EHEA_BMASK_SET(H_ALL_RES_QP_MAX_R3SGE,
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init_attr->wqe_size_enc_rq3);
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u64 r11_in =
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EHEA_BMASK_SET(H_ALL_RES_QP_SWQE_IDL, init_attr->swqe_imm_data_len)
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| EHEA_BMASK_SET(H_ALL_RES_QP_PORT_NUM, init_attr->port_nr);
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u64 threshold =
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EHEA_BMASK_SET(H_ALL_RES_QP_TH_RQ2, init_attr->rq2_threshold)
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| EHEA_BMASK_SET(H_ALL_RES_QP_TH_RQ3, init_attr->rq3_threshold);
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u64 r5_out = 0;
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u64 r6_out = 0;
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u64 r7_out = 0;
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u64 r8_out = 0;
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u64 r9_out = 0;
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u64 g_la_user_out = 0;
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u64 r11_out = 0;
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u64 r12_out = 0;
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hret = ehea_hcall_9arg_9ret(H_ALLOC_HEA_RESOURCE,
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adapter_handle, /* R4 */
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allocate_controls, /* R5 */
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init_attr->send_cq_handle, /* R6 */
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init_attr->recv_cq_handle, /* R7 */
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init_attr->aff_eq_handle, /* R8 */
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r9_reg, /* R9 */
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max_r10_reg, /* R10 */
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r11_in, /* R11 */
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threshold, /* R12 */
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qp_handle, /* R4 */
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&r5_out, /* R5 */
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&r6_out, /* R6 */
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&r7_out, /* R7 */
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&r8_out, /* R8 */
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&r9_out, /* R9 */
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&g_la_user_out, /* R10 */
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&r11_out, /* R11 */
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&r12_out); /* R12 */
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init_attr->qp_nr = (u32)r5_out;
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init_attr->act_nr_send_wqes =
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(u16)EHEA_BMASK_GET(H_ALL_RES_QP_ACT_SWQE, r6_out);
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init_attr->act_nr_rwqes_rq1 =
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(u16)EHEA_BMASK_GET(H_ALL_RES_QP_ACT_R1WQE, r6_out);
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init_attr->act_nr_rwqes_rq2 =
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(u16)EHEA_BMASK_GET(H_ALL_RES_QP_ACT_R2WQE, r6_out);
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init_attr->act_nr_rwqes_rq3 =
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(u16)EHEA_BMASK_GET(H_ALL_RES_QP_ACT_R3WQE, r6_out);
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init_attr->act_wqe_size_enc_sq = init_attr->wqe_size_enc_sq;
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init_attr->act_wqe_size_enc_rq1 = init_attr->wqe_size_enc_rq1;
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init_attr->act_wqe_size_enc_rq2 = init_attr->wqe_size_enc_rq2;
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init_attr->act_wqe_size_enc_rq3 = init_attr->wqe_size_enc_rq3;
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init_attr->nr_sq_pages =
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(u32)EHEA_BMASK_GET(H_ALL_RES_QP_SIZE_SQ, r8_out);
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init_attr->nr_rq1_pages =
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(u32)EHEA_BMASK_GET(H_ALL_RES_QP_SIZE_RQ1, r8_out);
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init_attr->nr_rq2_pages =
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(u32)EHEA_BMASK_GET(H_ALL_RES_QP_SIZE_RQ2, r9_out);
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init_attr->nr_rq3_pages =
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(u32)EHEA_BMASK_GET(H_ALL_RES_QP_SIZE_RQ3, r9_out);
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init_attr->liobn_sq =
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(u32)EHEA_BMASK_GET(H_ALL_RES_QP_LIOBN_SQ, r11_out);
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init_attr->liobn_rq1 =
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(u32)EHEA_BMASK_GET(H_ALL_RES_QP_LIOBN_RQ1, r11_out);
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init_attr->liobn_rq2 =
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(u32)EHEA_BMASK_GET(H_ALL_RES_QP_LIOBN_RQ2, r12_out);
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init_attr->liobn_rq3 =
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(u32)EHEA_BMASK_GET(H_ALL_RES_QP_LIOBN_RQ3, r12_out);
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if (!hret)
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hcp_epas_ctor(h_epas, g_la_user_out, g_la_user_out);
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return hret;
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}
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u64 ehea_h_alloc_resource_cq(const u64 adapter_handle,
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struct ehea_cq_attr *cq_attr,
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u64 *cq_handle, struct h_epas *epas)
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{
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u64 hret, dummy, act_nr_of_cqes_out, act_pages_out;
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u64 g_la_privileged_out, g_la_user_out;
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hret = ehea_hcall_9arg_9ret(H_ALLOC_HEA_RESOURCE,
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adapter_handle, /* R4 */
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H_ALL_RES_TYPE_CQ, /* R5 */
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cq_attr->eq_handle, /* R6 */
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cq_attr->cq_token, /* R7 */
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cq_attr->max_nr_of_cqes, /* R8 */
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0, 0, 0, 0, /* R9-R12 */
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cq_handle, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&act_nr_of_cqes_out, /* R7 */
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&act_pages_out, /* R8 */
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&g_la_privileged_out, /* R9 */
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&g_la_user_out, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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cq_attr->act_nr_of_cqes = act_nr_of_cqes_out;
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cq_attr->nr_pages = act_pages_out;
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if (!hret)
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hcp_epas_ctor(epas, g_la_privileged_out, g_la_user_out);
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return hret;
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}
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/* Defines for H_CALL H_ALLOC_RESOURCE */
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#define H_ALL_RES_TYPE_QP 1
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#define H_ALL_RES_TYPE_CQ 2
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#define H_ALL_RES_TYPE_EQ 3
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#define H_ALL_RES_TYPE_MR 5
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#define H_ALL_RES_TYPE_MW 6
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/* input param R5 */
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#define H_ALL_RES_EQ_NEQ EHEA_BMASK_IBM(0, 0)
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#define H_ALL_RES_EQ_NON_NEQ_ISN EHEA_BMASK_IBM(6, 7)
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#define H_ALL_RES_EQ_INH_EQE_GEN EHEA_BMASK_IBM(16, 16)
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#define H_ALL_RES_EQ_RES_TYPE EHEA_BMASK_IBM(56, 63)
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/* input param R6 */
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#define H_ALL_RES_EQ_MAX_EQE EHEA_BMASK_IBM(32, 63)
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/* output param R6 */
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#define H_ALL_RES_EQ_LIOBN EHEA_BMASK_IBM(32, 63)
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/* output param R7 */
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#define H_ALL_RES_EQ_ACT_EQE EHEA_BMASK_IBM(32, 63)
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/* output param R8 */
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#define H_ALL_RES_EQ_ACT_PS EHEA_BMASK_IBM(32, 63)
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/* output param R9 */
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#define H_ALL_RES_EQ_ACT_EQ_IST_C EHEA_BMASK_IBM(30, 31)
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#define H_ALL_RES_EQ_ACT_EQ_IST_1 EHEA_BMASK_IBM(40, 63)
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/* output param R10 */
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#define H_ALL_RES_EQ_ACT_EQ_IST_2 EHEA_BMASK_IBM(40, 63)
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/* output param R11 */
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#define H_ALL_RES_EQ_ACT_EQ_IST_3 EHEA_BMASK_IBM(40, 63)
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/* output param R12 */
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#define H_ALL_RES_EQ_ACT_EQ_IST_4 EHEA_BMASK_IBM(40, 63)
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u64 ehea_h_alloc_resource_eq(const u64 adapter_handle,
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struct ehea_eq_attr *eq_attr, u64 *eq_handle)
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{
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u64 hret, dummy, eq_liobn, allocate_controls;
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u64 ist1_out, ist2_out, ist3_out, ist4_out;
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u64 act_nr_of_eqes_out, act_pages_out;
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/* resource type */
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allocate_controls =
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EHEA_BMASK_SET(H_ALL_RES_EQ_RES_TYPE, H_ALL_RES_TYPE_EQ)
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| EHEA_BMASK_SET(H_ALL_RES_EQ_NEQ, eq_attr->type ? 1 : 0)
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| EHEA_BMASK_SET(H_ALL_RES_EQ_INH_EQE_GEN, !eq_attr->eqe_gen)
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| EHEA_BMASK_SET(H_ALL_RES_EQ_NON_NEQ_ISN, 1);
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hret = ehea_hcall_9arg_9ret(H_ALLOC_HEA_RESOURCE,
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adapter_handle, /* R4 */
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allocate_controls, /* R5 */
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eq_attr->max_nr_of_eqes, /* R6 */
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0, 0, 0, 0, 0, 0, /* R7-R10 */
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eq_handle, /* R4 */
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&dummy, /* R5 */
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&eq_liobn, /* R6 */
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&act_nr_of_eqes_out, /* R7 */
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&act_pages_out, /* R8 */
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&ist1_out, /* R9 */
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&ist2_out, /* R10 */
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&ist3_out, /* R11 */
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&ist4_out); /* R12 */
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eq_attr->act_nr_of_eqes = act_nr_of_eqes_out;
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eq_attr->nr_pages = act_pages_out;
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eq_attr->ist1 = ist1_out;
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eq_attr->ist2 = ist2_out;
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eq_attr->ist3 = ist3_out;
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eq_attr->ist4 = ist4_out;
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return hret;
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}
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u64 ehea_h_modify_ehea_qp(const u64 adapter_handle, const u8 cat,
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const u64 qp_handle, const u64 sel_mask,
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void *cb_addr, u64 *inv_attr_id, u64 *proc_mask,
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u16 *out_swr, u16 *out_rwr)
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{
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u64 hret, dummy, act_out_swr, act_out_rwr;
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if ((((u64)cb_addr) & (PAGE_SIZE - 1)) != 0) {
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ehea_error("not on page boundary");
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return H_PARAMETER;
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}
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hret = ehea_hcall_9arg_9ret(H_MODIFY_HEA_QP,
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adapter_handle, /* R4 */
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(u64) cat, /* R5 */
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qp_handle, /* R6 */
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sel_mask, /* R7 */
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virt_to_abs(cb_addr), /* R8 */
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0, 0, 0, 0, /* R9-R12 */
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inv_attr_id, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&act_out_swr, /* R7 */
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&act_out_rwr, /* R8 */
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proc_mask, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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*out_swr = act_out_swr;
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*out_rwr = act_out_rwr;
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return hret;
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}
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u64 ehea_h_register_rpage(const u64 adapter_handle, const u8 pagesize,
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const u8 queue_type, const u64 resource_handle,
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const u64 log_pageaddr, u64 count)
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{
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u64 dummy, reg_control;
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reg_control = EHEA_BMASK_SET(H_REG_RPAGE_PAGE_SIZE, pagesize)
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| EHEA_BMASK_SET(H_REG_RPAGE_QT, queue_type);
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return ehea_hcall_9arg_9ret(H_REGISTER_HEA_RPAGES,
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adapter_handle, /* R4 */
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reg_control, /* R5 */
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resource_handle, /* R6 */
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log_pageaddr, /* R7 */
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count, /* R8 */
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0, 0, 0, 0, /* R9-R12 */
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&dummy, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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}
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u64 ehea_h_register_smr(const u64 adapter_handle, const u64 orig_mr_handle,
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const u64 vaddr_in, const u32 access_ctrl, const u32 pd,
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struct ehea_mr *mr)
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{
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u64 hret, dummy, lkey_out;
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hret = ehea_hcall_9arg_9ret(H_REGISTER_SMR,
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adapter_handle , /* R4 */
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orig_mr_handle, /* R5 */
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vaddr_in, /* R6 */
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(((u64)access_ctrl) << 32ULL), /* R7 */
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pd, /* R8 */
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0, 0, 0, 0, /* R9-R12 */
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&mr->handle, /* R4 */
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&dummy, /* R5 */
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&lkey_out, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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mr->lkey = (u32)lkey_out;
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return hret;
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}
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u64 ehea_h_disable_and_get_hea(const u64 adapter_handle, const u64 qp_handle)
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{
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u64 hret, dummy, ladr_next_sq_wqe_out;
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u64 ladr_next_rq1_wqe_out, ladr_next_rq2_wqe_out, ladr_next_rq3_wqe_out;
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hret = ehea_hcall_9arg_9ret(H_DISABLE_AND_GET_HEA,
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adapter_handle, /* R4 */
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H_DISABLE_GET_EHEA_WQE_P, /* R5 */
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qp_handle, /* R6 */
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0, 0, 0, 0, 0, 0, /* R7-R12 */
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&ladr_next_sq_wqe_out, /* R4 */
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&ladr_next_rq1_wqe_out, /* R5 */
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&ladr_next_rq2_wqe_out, /* R6 */
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&ladr_next_rq3_wqe_out, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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return hret;
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}
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u64 ehea_h_free_resource(const u64 adapter_handle, const u64 res_handle)
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{
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u64 dummy;
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return ehea_hcall_9arg_9ret(H_FREE_RESOURCE,
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adapter_handle, /* R4 */
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res_handle, /* R5 */
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0, 0, 0, 0, 0, 0, 0, /* R6-R12 */
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&dummy, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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}
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u64 ehea_h_alloc_resource_mr(const u64 adapter_handle, const u64 vaddr,
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const u64 length, const u32 access_ctrl,
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const u32 pd, u64 *mr_handle, u32 *lkey)
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{
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u64 hret, dummy, lkey_out;
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hret = ehea_hcall_9arg_9ret(H_ALLOC_HEA_RESOURCE,
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adapter_handle, /* R4 */
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5, /* R5 */
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vaddr, /* R6 */
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length, /* R7 */
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(((u64) access_ctrl) << 32ULL),/* R8 */
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pd, /* R9 */
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0, 0, 0, /* R10-R12 */
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mr_handle, /* R4 */
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&dummy, /* R5 */
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&lkey_out, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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*lkey = (u32) lkey_out;
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return hret;
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}
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u64 ehea_h_register_rpage_mr(const u64 adapter_handle, const u64 mr_handle,
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const u8 pagesize, const u8 queue_type,
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const u64 log_pageaddr, const u64 count)
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{
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if ((count > 1) && (log_pageaddr & 0xfff)) {
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ehea_error("not on pageboundary");
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return H_PARAMETER;
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}
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return ehea_h_register_rpage(adapter_handle, pagesize,
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queue_type, mr_handle,
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log_pageaddr, count);
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}
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u64 ehea_h_query_ehea(const u64 adapter_handle, void *cb_addr)
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{
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u64 hret, dummy, cb_logaddr;
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cb_logaddr = virt_to_abs(cb_addr);
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hret = ehea_hcall_9arg_9ret(H_QUERY_HEA,
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adapter_handle, /* R4 */
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cb_logaddr, /* R5 */
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0, 0, 0, 0, 0, 0, 0, /* R6-R12 */
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&dummy, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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#ifdef DEBUG
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ehea_dmp(cb_addr, sizeof(struct hcp_query_ehea), "hcp_query_ehea");
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#endif
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return hret;
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}
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u64 ehea_h_query_ehea_port(const u64 adapter_handle, const u16 port_num,
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const u8 cb_cat, const u64 select_mask,
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void *cb_addr)
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{
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u64 port_info, dummy;
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u64 cb_logaddr = virt_to_abs(cb_addr);
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u64 arr_index = 0;
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port_info = EHEA_BMASK_SET(H_MEHEAPORT_CAT, cb_cat)
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| EHEA_BMASK_SET(H_MEHEAPORT_PN, port_num);
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return ehea_hcall_9arg_9ret(H_QUERY_HEA_PORT,
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adapter_handle, /* R4 */
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port_info, /* R5 */
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select_mask, /* R6 */
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arr_index, /* R7 */
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cb_logaddr, /* R8 */
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0, 0, 0, 0, /* R9-R12 */
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&dummy, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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}
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u64 ehea_h_modify_ehea_port(const u64 adapter_handle, const u16 port_num,
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const u8 cb_cat, const u64 select_mask,
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void *cb_addr)
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{
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u64 port_info, dummy, inv_attr_ident, proc_mask;
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u64 arr_index = 0;
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u64 cb_logaddr = virt_to_abs(cb_addr);
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port_info = EHEA_BMASK_SET(H_MEHEAPORT_CAT, cb_cat)
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| EHEA_BMASK_SET(H_MEHEAPORT_PN, port_num);
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#ifdef DEBUG
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ehea_dump(cb_addr, sizeof(struct hcp_ehea_port_cb0), "Before HCALL");
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#endif
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return ehea_hcall_9arg_9ret(H_MODIFY_HEA_PORT,
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adapter_handle, /* R4 */
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port_info, /* R5 */
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select_mask, /* R6 */
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arr_index, /* R7 */
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cb_logaddr, /* R8 */
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0, 0, 0, 0, /* R9-R12 */
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&inv_attr_ident, /* R4 */
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&proc_mask, /* R5 */
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&dummy, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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}
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u64 ehea_h_reg_dereg_bcmc(const u64 adapter_handle, const u16 port_num,
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const u8 reg_type, const u64 mc_mac_addr,
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const u16 vlan_id, const u32 hcall_id)
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{
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u64 r5_port_num, r6_reg_type, r7_mc_mac_addr, r8_vlan_id, dummy;
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u64 mac_addr = mc_mac_addr >> 16;
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r5_port_num = EHEA_BMASK_SET(H_REGBCMC_PN, port_num);
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r6_reg_type = EHEA_BMASK_SET(H_REGBCMC_REGTYPE, reg_type);
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r7_mc_mac_addr = EHEA_BMASK_SET(H_REGBCMC_MACADDR, mac_addr);
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r8_vlan_id = EHEA_BMASK_SET(H_REGBCMC_VLANID, vlan_id);
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return ehea_hcall_9arg_9ret(hcall_id,
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adapter_handle, /* R4 */
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r5_port_num, /* R5 */
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r6_reg_type, /* R6 */
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r7_mc_mac_addr, /* R7 */
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r8_vlan_id, /* R8 */
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0, 0, 0, 0, /* R9-R12 */
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&dummy, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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}
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u64 ehea_h_reset_events(const u64 adapter_handle, const u64 neq_handle,
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const u64 event_mask)
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{
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u64 dummy;
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return ehea_hcall_9arg_9ret(H_RESET_EVENTS,
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adapter_handle, /* R4 */
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neq_handle, /* R5 */
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event_mask, /* R6 */
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0, 0, 0, 0, 0, 0, /* R7-R12 */
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&dummy, /* R4 */
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&dummy, /* R5 */
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&dummy, /* R6 */
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&dummy, /* R7 */
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&dummy, /* R8 */
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&dummy, /* R9 */
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&dummy, /* R10 */
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&dummy, /* R11 */
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&dummy); /* R12 */
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}
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