![Laurent Pinchart](/assets/img/avatar_default.png)
Source components in the display pipeline need to configure their output signals polarities and clock driving edge based on the requirements of the sink component. Those requirements are currently shared across the whole pipeline in the flags of a videomode structure, instead of being local to each bus. This both prevents multiple buses from having different configurations (when the hardware supports it), and makes it difficult to move from videomode to drm_display_mode as the latter doesn't contain bus polarities and clock edge flags. Add a bus_flags field to the omap_dss_device structure and move the DISPLAY_FLAGS_DE_(LOW|HIGH), DISPLAY_FLAGS_PIXDATA_(POS|NEG)EDGE and DISPLAY_FLAGS_SYNC_(POS|NEG)EDGE videomode flags to bus_flags in all external encoders, connectors and panels. The videomode flags are still used internally for internal encoders, this will be addressed in a second step. The related videomode flags in the default mode of the DVI connector can simply be dropped, as they are always overridden by the TFP410 driver. Note that this results in both the DISPLAY_FLAGS_SYNC_POSEDGE and DISPLAY_FLAGS_SYNC_NEGEDGE flags being set, which is invalid, but only the former is tested for when programming the DISPC, so the DVI connector flags are effectively overridden by the TFP410 flags. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
388 lines
8.5 KiB
C
388 lines
8.5 KiB
C
/*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "SDI"
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/regulator/consumer.h>
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#include <linux/export.h>
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#include <linux/platform_device.h>
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#include <linux/string.h>
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#include <linux/of.h>
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#include "omapdss.h"
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#include "dss.h"
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struct sdi_device {
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struct platform_device *pdev;
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struct dss_device *dss;
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bool update_enabled;
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struct regulator *vdds_sdi_reg;
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struct dss_lcd_mgr_config mgr_config;
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struct videomode vm;
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int datapairs;
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struct omap_dss_device output;
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};
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#define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output)
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struct sdi_clk_calc_ctx {
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struct sdi_device *sdi;
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unsigned long pck_min, pck_max;
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unsigned long fck;
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struct dispc_clock_info dispc_cinfo;
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};
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static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
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unsigned long pck, void *data)
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{
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struct sdi_clk_calc_ctx *ctx = data;
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ctx->dispc_cinfo.lck_div = lckd;
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ctx->dispc_cinfo.pck_div = pckd;
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ctx->dispc_cinfo.lck = lck;
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ctx->dispc_cinfo.pck = pck;
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return true;
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}
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static bool dpi_calc_dss_cb(unsigned long fck, void *data)
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{
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struct sdi_clk_calc_ctx *ctx = data;
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ctx->fck = fck;
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return dispc_div_calc(ctx->sdi->dss->dispc, fck,
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ctx->pck_min, ctx->pck_max,
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dpi_calc_dispc_cb, ctx);
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}
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static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk,
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unsigned long *fck,
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struct dispc_clock_info *dispc_cinfo)
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{
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int i;
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struct sdi_clk_calc_ctx ctx;
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/*
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* DSS fclk gives us very few possibilities, so finding a good pixel
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* clock may not be possible. We try multiple times to find the clock,
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* each time widening the pixel clock range we look for, up to
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* +/- 1MHz.
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*/
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for (i = 0; i < 10; ++i) {
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bool ok;
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memset(&ctx, 0, sizeof(ctx));
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ctx.sdi = sdi;
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if (pclk > 1000 * i * i * i)
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ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
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else
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ctx.pck_min = 0;
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ctx.pck_max = pclk + 1000 * i * i * i;
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ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min,
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dpi_calc_dss_cb, &ctx);
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if (ok) {
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*fck = ctx.fck;
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*dispc_cinfo = ctx.dispc_cinfo;
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return 0;
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}
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}
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return -EINVAL;
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}
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static void sdi_config_lcd_manager(struct sdi_device *sdi)
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{
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sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
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sdi->mgr_config.stallmode = false;
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sdi->mgr_config.fifohandcheck = false;
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sdi->mgr_config.video_port_width = 24;
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sdi->mgr_config.lcden_sig_polarity = 1;
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dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config);
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}
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static int sdi_display_enable(struct omap_dss_device *dssdev)
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{
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struct sdi_device *sdi = dssdev_to_sdi(dssdev);
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struct videomode *vm = &sdi->vm;
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unsigned long fck;
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struct dispc_clock_info dispc_cinfo;
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unsigned long pck;
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int r;
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if (!sdi->output.dispc_channel_connected) {
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DSSERR("failed to enable display: no output/manager\n");
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return -ENODEV;
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}
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r = regulator_enable(sdi->vdds_sdi_reg);
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if (r)
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goto err_reg_enable;
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r = dispc_runtime_get(sdi->dss->dispc);
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if (r)
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goto err_get_dispc;
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r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo);
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if (r)
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goto err_calc_clock_div;
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sdi->mgr_config.clock_info = dispc_cinfo;
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pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
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if (pck != vm->pixelclock) {
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DSSWARN("Could not find exact pixel clock. Requested %lu Hz, got %lu Hz\n",
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vm->pixelclock, pck);
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vm->pixelclock = pck;
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}
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dss_mgr_set_timings(&sdi->output, vm);
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r = dss_set_fck_rate(sdi->dss, fck);
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if (r)
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goto err_set_dss_clock_div;
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sdi_config_lcd_manager(sdi);
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/*
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* LCLK and PCLK divisors are located in shadow registers, and we
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* normally write them to DISPC registers when enabling the output.
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* However, SDI uses pck-free as source clock for its PLL, and pck-free
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* is affected by the divisors. And as we need the PLL before enabling
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* the output, we need to write the divisors early.
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*
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* It seems just writing to the DISPC register is enough, and we don't
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* need to care about the shadow register mechanism for pck-free. The
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* exact reason for this is unknown.
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*/
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dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
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&sdi->mgr_config.clock_info);
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dss_sdi_init(sdi->dss, sdi->datapairs);
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r = dss_sdi_enable(sdi->dss);
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if (r)
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goto err_sdi_enable;
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mdelay(2);
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r = dss_mgr_enable(&sdi->output);
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if (r)
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goto err_mgr_enable;
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return 0;
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err_mgr_enable:
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dss_sdi_disable(sdi->dss);
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err_sdi_enable:
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err_set_dss_clock_div:
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err_calc_clock_div:
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dispc_runtime_put(sdi->dss->dispc);
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err_get_dispc:
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regulator_disable(sdi->vdds_sdi_reg);
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err_reg_enable:
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return r;
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}
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static void sdi_display_disable(struct omap_dss_device *dssdev)
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{
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struct sdi_device *sdi = dssdev_to_sdi(dssdev);
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dss_mgr_disable(&sdi->output);
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dss_sdi_disable(sdi->dss);
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dispc_runtime_put(sdi->dss->dispc);
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regulator_disable(sdi->vdds_sdi_reg);
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}
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static void sdi_set_timings(struct omap_dss_device *dssdev,
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const struct videomode *vm)
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{
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struct sdi_device *sdi = dssdev_to_sdi(dssdev);
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sdi->vm = *vm;
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}
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static int sdi_check_timings(struct omap_dss_device *dssdev,
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struct videomode *vm)
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{
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struct sdi_device *sdi = dssdev_to_sdi(dssdev);
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enum omap_channel channel = dssdev->dispc_channel;
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if (!dispc_mgr_timings_ok(sdi->dss->dispc, channel, vm))
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return -EINVAL;
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if (vm->pixelclock == 0)
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return -EINVAL;
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return 0;
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}
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static int sdi_connect(struct omap_dss_device *src,
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struct omap_dss_device *dst)
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{
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int r;
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r = omapdss_device_connect(dst->dss, dst, dst->next);
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if (r)
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return r;
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dst->dispc_channel_connected = true;
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return 0;
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}
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static void sdi_disconnect(struct omap_dss_device *src,
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struct omap_dss_device *dst)
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{
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dst->dispc_channel_connected = false;
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omapdss_device_disconnect(dst, dst->next);
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}
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static const struct omap_dss_device_ops sdi_ops = {
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.connect = sdi_connect,
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.disconnect = sdi_disconnect,
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.enable = sdi_display_enable,
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.disable = sdi_display_disable,
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.check_timings = sdi_check_timings,
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.set_timings = sdi_set_timings,
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};
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static int sdi_init_output(struct sdi_device *sdi)
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{
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struct omap_dss_device *out = &sdi->output;
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int r;
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out->dev = &sdi->pdev->dev;
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out->id = OMAP_DSS_OUTPUT_SDI;
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out->output_type = OMAP_DISPLAY_TYPE_SDI;
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out->name = "sdi.0";
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out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
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/* We have SDI only on OMAP3, where it's on port 1 */
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out->of_ports = BIT(1);
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out->ops = &sdi_ops;
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out->owner = THIS_MODULE;
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out->bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE /* 15.5.9.1.2 */
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| DRM_BUS_FLAG_SYNC_POSEDGE;
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out->next = omapdss_of_find_connected_device(out->dev->of_node, 1);
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if (IS_ERR(out->next)) {
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if (PTR_ERR(out->next) != -EPROBE_DEFER)
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dev_err(out->dev, "failed to find video sink\n");
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return PTR_ERR(out->next);
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}
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r = omapdss_output_validate(out);
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if (r) {
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omapdss_device_put(out->next);
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out->next = NULL;
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return r;
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}
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omapdss_device_register(out);
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return 0;
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}
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static void sdi_uninit_output(struct sdi_device *sdi)
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{
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if (sdi->output.next)
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omapdss_device_put(sdi->output.next);
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omapdss_device_unregister(&sdi->output);
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}
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int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
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struct device_node *port)
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{
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struct sdi_device *sdi;
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struct device_node *ep;
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u32 datapairs;
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int r;
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sdi = kzalloc(sizeof(*sdi), GFP_KERNEL);
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if (!sdi)
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return -ENOMEM;
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ep = of_get_next_child(port, NULL);
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if (!ep) {
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r = 0;
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goto err_free;
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}
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r = of_property_read_u32(ep, "datapairs", &datapairs);
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of_node_put(ep);
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if (r) {
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DSSERR("failed to parse datapairs\n");
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goto err_free;
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}
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sdi->datapairs = datapairs;
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sdi->dss = dss;
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sdi->pdev = pdev;
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port->data = sdi;
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sdi->vdds_sdi_reg = devm_regulator_get(&pdev->dev, "vdds_sdi");
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if (IS_ERR(sdi->vdds_sdi_reg)) {
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r = PTR_ERR(sdi->vdds_sdi_reg);
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if (r != -EPROBE_DEFER)
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DSSERR("can't get VDDS_SDI regulator\n");
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goto err_free;
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}
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r = sdi_init_output(sdi);
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if (r)
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goto err_free;
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return 0;
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err_free:
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kfree(sdi);
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return r;
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}
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void sdi_uninit_port(struct device_node *port)
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{
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struct sdi_device *sdi = port->data;
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if (!sdi)
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return;
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sdi_uninit_output(sdi);
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kfree(sdi);
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}
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