![Laurent Pinchart](/assets/img/avatar_default.png)
Timings for the TV output are currently reported by the analog TV connector. This has the disadvantage of having to handle timing-related operations in a connector omap_dss_device that has, at the hardware level, no knowledge of any timing information. Implement the .get_timings() operation in the venc driver, and get timings from the first component in the pipeline that implements the operatation. This switches the duty of reporting analog TV timings from the connector to the encoder. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
1000 lines
24 KiB
C
1000 lines
24 KiB
C
/*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*
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* VENC settings from TI's DSS driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "VENC"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/mutex.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/seq_file.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_graph.h>
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#include <linux/component.h>
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#include <linux/sys_soc.h>
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#include "omapdss.h"
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#include "dss.h"
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/* Venc registers */
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#define VENC_REV_ID 0x00
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#define VENC_STATUS 0x04
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#define VENC_F_CONTROL 0x08
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#define VENC_VIDOUT_CTRL 0x10
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#define VENC_SYNC_CTRL 0x14
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#define VENC_LLEN 0x1C
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#define VENC_FLENS 0x20
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#define VENC_HFLTR_CTRL 0x24
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#define VENC_CC_CARR_WSS_CARR 0x28
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#define VENC_C_PHASE 0x2C
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#define VENC_GAIN_U 0x30
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#define VENC_GAIN_V 0x34
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#define VENC_GAIN_Y 0x38
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#define VENC_BLACK_LEVEL 0x3C
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#define VENC_BLANK_LEVEL 0x40
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#define VENC_X_COLOR 0x44
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#define VENC_M_CONTROL 0x48
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#define VENC_BSTAMP_WSS_DATA 0x4C
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#define VENC_S_CARR 0x50
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#define VENC_LINE21 0x54
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#define VENC_LN_SEL 0x58
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#define VENC_L21__WC_CTL 0x5C
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#define VENC_HTRIGGER_VTRIGGER 0x60
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#define VENC_SAVID__EAVID 0x64
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#define VENC_FLEN__FAL 0x68
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#define VENC_LAL__PHASE_RESET 0x6C
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#define VENC_HS_INT_START_STOP_X 0x70
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#define VENC_HS_EXT_START_STOP_X 0x74
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#define VENC_VS_INT_START_X 0x78
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#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
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#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
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#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
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#define VENC_VS_EXT_STOP_Y 0x88
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#define VENC_AVID_START_STOP_X 0x90
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#define VENC_AVID_START_STOP_Y 0x94
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#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
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#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
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#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
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#define VENC_TVDETGP_INT_START_STOP_X 0xB0
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#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
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#define VENC_GEN_CTRL 0xB8
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#define VENC_OUTPUT_CONTROL 0xC4
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#define VENC_OUTPUT_TEST 0xC8
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#define VENC_DAC_B__DAC_C 0xC8
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struct venc_config {
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u32 f_control;
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u32 vidout_ctrl;
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u32 sync_ctrl;
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u32 llen;
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u32 flens;
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u32 hfltr_ctrl;
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u32 cc_carr_wss_carr;
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u32 c_phase;
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u32 gain_u;
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u32 gain_v;
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u32 gain_y;
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u32 black_level;
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u32 blank_level;
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u32 x_color;
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u32 m_control;
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u32 bstamp_wss_data;
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u32 s_carr;
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u32 line21;
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u32 ln_sel;
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u32 l21__wc_ctl;
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u32 htrigger_vtrigger;
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u32 savid__eavid;
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u32 flen__fal;
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u32 lal__phase_reset;
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u32 hs_int_start_stop_x;
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u32 hs_ext_start_stop_x;
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u32 vs_int_start_x;
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u32 vs_int_stop_x__vs_int_start_y;
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u32 vs_int_stop_y__vs_ext_start_x;
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u32 vs_ext_stop_x__vs_ext_start_y;
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u32 vs_ext_stop_y;
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u32 avid_start_stop_x;
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u32 avid_start_stop_y;
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u32 fid_int_start_x__fid_int_start_y;
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u32 fid_int_offset_y__fid_ext_start_x;
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u32 fid_ext_start_y__fid_ext_offset_y;
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u32 tvdetgp_int_start_stop_x;
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u32 tvdetgp_int_start_stop_y;
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u32 gen_ctrl;
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};
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/* from TRM */
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static const struct venc_config venc_config_pal_trm = {
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.f_control = 0,
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.vidout_ctrl = 1,
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.sync_ctrl = 0x40,
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.llen = 0x35F, /* 863 */
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.flens = 0x270, /* 624 */
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.hfltr_ctrl = 0,
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.cc_carr_wss_carr = 0x2F7225ED,
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.c_phase = 0,
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.gain_u = 0x111,
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.gain_v = 0x181,
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.gain_y = 0x140,
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.black_level = 0x3B,
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.blank_level = 0x3B,
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.x_color = 0x7,
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.m_control = 0x2,
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.bstamp_wss_data = 0x3F,
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.s_carr = 0x2A098ACB,
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.line21 = 0,
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.ln_sel = 0x01290015,
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.l21__wc_ctl = 0x0000F603,
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.htrigger_vtrigger = 0,
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.savid__eavid = 0x06A70108,
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.flen__fal = 0x00180270,
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.lal__phase_reset = 0x00040135,
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.hs_int_start_stop_x = 0x00880358,
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.hs_ext_start_stop_x = 0x000F035F,
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.vs_int_start_x = 0x01A70000,
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.vs_int_stop_x__vs_int_start_y = 0x000001A7,
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.vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
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.vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
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.vs_ext_stop_y = 0x00000025,
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.avid_start_stop_x = 0x03530083,
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.avid_start_stop_y = 0x026C002E,
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.fid_int_start_x__fid_int_start_y = 0x0001008A,
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.fid_int_offset_y__fid_ext_start_x = 0x002E0138,
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.fid_ext_start_y__fid_ext_offset_y = 0x01380001,
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.tvdetgp_int_start_stop_x = 0x00140001,
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.tvdetgp_int_start_stop_y = 0x00010001,
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.gen_ctrl = 0x00FF0000,
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};
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/* from TRM */
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static const struct venc_config venc_config_ntsc_trm = {
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.f_control = 0,
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.vidout_ctrl = 1,
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.sync_ctrl = 0x8040,
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.llen = 0x359,
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.flens = 0x20C,
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.hfltr_ctrl = 0,
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.cc_carr_wss_carr = 0x043F2631,
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.c_phase = 0,
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.gain_u = 0x102,
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.gain_v = 0x16C,
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.gain_y = 0x12F,
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.black_level = 0x43,
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.blank_level = 0x38,
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.x_color = 0x7,
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.m_control = 0x1,
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.bstamp_wss_data = 0x38,
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.s_carr = 0x21F07C1F,
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.line21 = 0,
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.ln_sel = 0x01310011,
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.l21__wc_ctl = 0x0000F003,
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.htrigger_vtrigger = 0,
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.savid__eavid = 0x069300F4,
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.flen__fal = 0x0016020C,
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.lal__phase_reset = 0x00060107,
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.hs_int_start_stop_x = 0x008E0350,
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.hs_ext_start_stop_x = 0x000F0359,
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.vs_int_start_x = 0x01A00000,
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.vs_int_stop_x__vs_int_start_y = 0x020701A0,
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.vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
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.vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
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.vs_ext_stop_y = 0x00000006,
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.avid_start_stop_x = 0x03480078,
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.avid_start_stop_y = 0x02060024,
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.fid_int_start_x__fid_int_start_y = 0x0001008A,
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.fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
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.fid_ext_start_y__fid_ext_offset_y = 0x01060006,
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.tvdetgp_int_start_stop_x = 0x00140001,
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.tvdetgp_int_start_stop_y = 0x00010001,
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.gen_ctrl = 0x00F90000,
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};
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static const struct venc_config venc_config_pal_bdghi = {
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.f_control = 0,
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.vidout_ctrl = 0,
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.sync_ctrl = 0,
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.hfltr_ctrl = 0,
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.x_color = 0,
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.line21 = 0,
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.ln_sel = 21,
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.htrigger_vtrigger = 0,
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.tvdetgp_int_start_stop_x = 0x00140001,
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.tvdetgp_int_start_stop_y = 0x00010001,
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.gen_ctrl = 0x00FB0000,
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.llen = 864-1,
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.flens = 625-1,
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.cc_carr_wss_carr = 0x2F7625ED,
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.c_phase = 0xDF,
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.gain_u = 0x111,
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.gain_v = 0x181,
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.gain_y = 0x140,
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.black_level = 0x3e,
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.blank_level = 0x3e,
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.m_control = 0<<2 | 1<<1,
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.bstamp_wss_data = 0x42,
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.s_carr = 0x2a098acb,
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.l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
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.savid__eavid = 0x06A70108,
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.flen__fal = 23<<16 | 624<<0,
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.lal__phase_reset = 2<<17 | 310<<0,
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.hs_int_start_stop_x = 0x00920358,
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.hs_ext_start_stop_x = 0x000F035F,
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.vs_int_start_x = 0x1a7<<16,
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.vs_int_stop_x__vs_int_start_y = 0x000601A7,
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.vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
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.vs_ext_stop_x__vs_ext_start_y = 0x27101af,
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.vs_ext_stop_y = 0x05,
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.avid_start_stop_x = 0x03530082,
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.avid_start_stop_y = 0x0270002E,
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.fid_int_start_x__fid_int_start_y = 0x0005008A,
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.fid_int_offset_y__fid_ext_start_x = 0x002E0138,
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.fid_ext_start_y__fid_ext_offset_y = 0x01380005,
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};
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enum venc_videomode {
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VENC_MODE_UNKNOWN,
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VENC_MODE_PAL,
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VENC_MODE_NTSC,
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};
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static const struct videomode omap_dss_pal_vm = {
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.hactive = 720,
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.vactive = 574,
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.pixelclock = 13500000,
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.hsync_len = 64,
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.hfront_porch = 12,
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.hback_porch = 68,
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.vsync_len = 5,
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.vfront_porch = 5,
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.vback_porch = 41,
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.flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
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DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
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DISPLAY_FLAGS_PIXDATA_POSEDGE |
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DISPLAY_FLAGS_SYNC_NEGEDGE,
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};
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static const struct videomode omap_dss_ntsc_vm = {
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.hactive = 720,
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.vactive = 482,
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.pixelclock = 13500000,
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.hsync_len = 64,
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.hfront_porch = 16,
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.hback_porch = 58,
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.vsync_len = 6,
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.vfront_porch = 6,
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.vback_porch = 31,
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.flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
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DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
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DISPLAY_FLAGS_PIXDATA_POSEDGE |
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DISPLAY_FLAGS_SYNC_NEGEDGE,
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};
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static enum venc_videomode venc_get_videomode(const struct videomode *vm)
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{
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if (!(vm->flags & DISPLAY_FLAGS_INTERLACED))
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return VENC_MODE_UNKNOWN;
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if (vm->pixelclock == omap_dss_pal_vm.pixelclock &&
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vm->hactive == omap_dss_pal_vm.hactive &&
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vm->vactive == omap_dss_pal_vm.vactive)
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return VENC_MODE_PAL;
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if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock &&
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vm->hactive == omap_dss_ntsc_vm.hactive &&
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vm->vactive == omap_dss_ntsc_vm.vactive)
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return VENC_MODE_NTSC;
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return VENC_MODE_UNKNOWN;
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}
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struct venc_device {
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struct platform_device *pdev;
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void __iomem *base;
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struct mutex venc_lock;
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u32 wss_data;
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struct regulator *vdda_dac_reg;
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struct dss_device *dss;
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struct dss_debugfs_entry *debugfs;
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struct clk *tv_dac_clk;
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struct videomode vm;
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enum omap_dss_venc_type type;
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bool invert_polarity;
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bool requires_tv_dac_clk;
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struct omap_dss_device output;
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};
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#define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output)
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static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
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{
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__raw_writel(val, venc->base + idx);
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}
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static inline u32 venc_read_reg(struct venc_device *venc, int idx)
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{
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u32 l = __raw_readl(venc->base + idx);
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return l;
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}
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static void venc_write_config(struct venc_device *venc,
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const struct venc_config *config)
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{
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DSSDBG("write venc conf\n");
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venc_write_reg(venc, VENC_LLEN, config->llen);
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venc_write_reg(venc, VENC_FLENS, config->flens);
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venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
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venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
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venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
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venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
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venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
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venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
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venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
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venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
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venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
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venc->wss_data);
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venc_write_reg(venc, VENC_S_CARR, config->s_carr);
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venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
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venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
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venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
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venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
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venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
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config->hs_int_start_stop_x);
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venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
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config->hs_ext_start_stop_x);
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venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
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venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
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config->vs_int_stop_x__vs_int_start_y);
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venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
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config->vs_int_stop_y__vs_ext_start_x);
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venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
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config->vs_ext_stop_x__vs_ext_start_y);
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venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
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venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
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venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
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venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
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config->fid_int_start_x__fid_int_start_y);
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venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
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config->fid_int_offset_y__fid_ext_start_x);
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venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
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config->fid_ext_start_y__fid_ext_offset_y);
|
|
|
|
venc_write_reg(venc, VENC_DAC_B__DAC_C,
|
|
venc_read_reg(venc, VENC_DAC_B__DAC_C));
|
|
venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
|
|
venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
|
|
venc_write_reg(venc, VENC_X_COLOR, config->x_color);
|
|
venc_write_reg(venc, VENC_LINE21, config->line21);
|
|
venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
|
|
venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
|
|
venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
|
|
config->tvdetgp_int_start_stop_x);
|
|
venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
|
|
config->tvdetgp_int_start_stop_y);
|
|
venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
|
|
venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
|
|
venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
|
|
}
|
|
|
|
static void venc_reset(struct venc_device *venc)
|
|
{
|
|
int t = 1000;
|
|
|
|
venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
|
|
while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
|
|
if (--t == 0) {
|
|
DSSERR("Failed to reset venc\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
|
|
/* the magical sleep that makes things work */
|
|
/* XXX more info? What bug this circumvents? */
|
|
msleep(20);
|
|
#endif
|
|
}
|
|
|
|
static int venc_runtime_get(struct venc_device *venc)
|
|
{
|
|
int r;
|
|
|
|
DSSDBG("venc_runtime_get\n");
|
|
|
|
r = pm_runtime_get_sync(&venc->pdev->dev);
|
|
WARN_ON(r < 0);
|
|
return r < 0 ? r : 0;
|
|
}
|
|
|
|
static void venc_runtime_put(struct venc_device *venc)
|
|
{
|
|
int r;
|
|
|
|
DSSDBG("venc_runtime_put\n");
|
|
|
|
r = pm_runtime_put_sync(&venc->pdev->dev);
|
|
WARN_ON(r < 0 && r != -ENOSYS);
|
|
}
|
|
|
|
static const struct venc_config *venc_timings_to_config(struct videomode *vm)
|
|
{
|
|
switch (venc_get_videomode(vm)) {
|
|
default:
|
|
WARN_ON_ONCE(1);
|
|
case VENC_MODE_PAL:
|
|
return &venc_config_pal_trm;
|
|
case VENC_MODE_NTSC:
|
|
return &venc_config_ntsc_trm;
|
|
}
|
|
}
|
|
|
|
static int venc_power_on(struct venc_device *venc)
|
|
{
|
|
u32 l;
|
|
int r;
|
|
|
|
r = venc_runtime_get(venc);
|
|
if (r)
|
|
goto err0;
|
|
|
|
venc_reset(venc);
|
|
venc_write_config(venc, venc_timings_to_config(&venc->vm));
|
|
|
|
dss_set_venc_output(venc->dss, venc->type);
|
|
dss_set_dac_pwrdn_bgz(venc->dss, 1);
|
|
|
|
l = 0;
|
|
|
|
if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
|
|
l |= 1 << 1;
|
|
else /* S-Video */
|
|
l |= (1 << 0) | (1 << 2);
|
|
|
|
if (venc->invert_polarity == false)
|
|
l |= 1 << 3;
|
|
|
|
venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
|
|
|
|
dss_mgr_set_timings(&venc->output, &venc->vm);
|
|
|
|
r = regulator_enable(venc->vdda_dac_reg);
|
|
if (r)
|
|
goto err1;
|
|
|
|
r = dss_mgr_enable(&venc->output);
|
|
if (r)
|
|
goto err2;
|
|
|
|
return 0;
|
|
|
|
err2:
|
|
regulator_disable(venc->vdda_dac_reg);
|
|
err1:
|
|
venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
|
|
dss_set_dac_pwrdn_bgz(venc->dss, 0);
|
|
|
|
venc_runtime_put(venc);
|
|
err0:
|
|
return r;
|
|
}
|
|
|
|
static void venc_power_off(struct venc_device *venc)
|
|
{
|
|
venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
|
|
dss_set_dac_pwrdn_bgz(venc->dss, 0);
|
|
|
|
dss_mgr_disable(&venc->output);
|
|
|
|
regulator_disable(venc->vdda_dac_reg);
|
|
|
|
venc_runtime_put(venc);
|
|
}
|
|
|
|
static int venc_display_enable(struct omap_dss_device *dssdev)
|
|
{
|
|
struct venc_device *venc = dssdev_to_venc(dssdev);
|
|
int r;
|
|
|
|
DSSDBG("venc_display_enable\n");
|
|
|
|
mutex_lock(&venc->venc_lock);
|
|
|
|
if (!dssdev->dispc_channel_connected) {
|
|
DSSERR("Failed to enable display: no output/manager\n");
|
|
r = -ENODEV;
|
|
goto err0;
|
|
}
|
|
|
|
r = venc_power_on(venc);
|
|
if (r)
|
|
goto err0;
|
|
|
|
venc->wss_data = 0;
|
|
|
|
mutex_unlock(&venc->venc_lock);
|
|
|
|
return 0;
|
|
err0:
|
|
mutex_unlock(&venc->venc_lock);
|
|
return r;
|
|
}
|
|
|
|
static void venc_display_disable(struct omap_dss_device *dssdev)
|
|
{
|
|
struct venc_device *venc = dssdev_to_venc(dssdev);
|
|
|
|
DSSDBG("venc_display_disable\n");
|
|
|
|
mutex_lock(&venc->venc_lock);
|
|
|
|
venc_power_off(venc);
|
|
|
|
mutex_unlock(&venc->venc_lock);
|
|
}
|
|
|
|
static void venc_get_timings(struct omap_dss_device *dssdev,
|
|
struct videomode *vm)
|
|
{
|
|
struct venc_device *venc = dssdev_to_venc(dssdev);
|
|
|
|
mutex_lock(&venc->venc_lock);
|
|
*vm = venc->vm;
|
|
mutex_unlock(&venc->venc_lock);
|
|
}
|
|
|
|
static void venc_set_timings(struct omap_dss_device *dssdev,
|
|
const struct videomode *vm)
|
|
{
|
|
struct venc_device *venc = dssdev_to_venc(dssdev);
|
|
struct videomode actual_vm;
|
|
|
|
DSSDBG("venc_set_timings\n");
|
|
|
|
mutex_lock(&venc->venc_lock);
|
|
|
|
switch (venc_get_videomode(vm)) {
|
|
default:
|
|
WARN_ON_ONCE(1);
|
|
case VENC_MODE_PAL:
|
|
actual_vm = omap_dss_pal_vm;
|
|
break;
|
|
case VENC_MODE_NTSC:
|
|
actual_vm = omap_dss_ntsc_vm;
|
|
break;
|
|
}
|
|
|
|
/* Reset WSS data when the TV standard changes. */
|
|
if (memcmp(&venc->vm, &actual_vm, sizeof(actual_vm)))
|
|
venc->wss_data = 0;
|
|
|
|
venc->vm = actual_vm;
|
|
|
|
dispc_set_tv_pclk(venc->dss->dispc, 13500000);
|
|
|
|
mutex_unlock(&venc->venc_lock);
|
|
}
|
|
|
|
static int venc_check_timings(struct omap_dss_device *dssdev,
|
|
struct videomode *vm)
|
|
{
|
|
DSSDBG("venc_check_timings\n");
|
|
|
|
switch (venc_get_videomode(vm)) {
|
|
case VENC_MODE_PAL:
|
|
case VENC_MODE_NTSC:
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int venc_dump_regs(struct seq_file *s, void *p)
|
|
{
|
|
struct venc_device *venc = s->private;
|
|
|
|
#define DUMPREG(venc, r) \
|
|
seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
|
|
|
|
if (venc_runtime_get(venc))
|
|
return 0;
|
|
|
|
DUMPREG(venc, VENC_F_CONTROL);
|
|
DUMPREG(venc, VENC_VIDOUT_CTRL);
|
|
DUMPREG(venc, VENC_SYNC_CTRL);
|
|
DUMPREG(venc, VENC_LLEN);
|
|
DUMPREG(venc, VENC_FLENS);
|
|
DUMPREG(venc, VENC_HFLTR_CTRL);
|
|
DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
|
|
DUMPREG(venc, VENC_C_PHASE);
|
|
DUMPREG(venc, VENC_GAIN_U);
|
|
DUMPREG(venc, VENC_GAIN_V);
|
|
DUMPREG(venc, VENC_GAIN_Y);
|
|
DUMPREG(venc, VENC_BLACK_LEVEL);
|
|
DUMPREG(venc, VENC_BLANK_LEVEL);
|
|
DUMPREG(venc, VENC_X_COLOR);
|
|
DUMPREG(venc, VENC_M_CONTROL);
|
|
DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
|
|
DUMPREG(venc, VENC_S_CARR);
|
|
DUMPREG(venc, VENC_LINE21);
|
|
DUMPREG(venc, VENC_LN_SEL);
|
|
DUMPREG(venc, VENC_L21__WC_CTL);
|
|
DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
|
|
DUMPREG(venc, VENC_SAVID__EAVID);
|
|
DUMPREG(venc, VENC_FLEN__FAL);
|
|
DUMPREG(venc, VENC_LAL__PHASE_RESET);
|
|
DUMPREG(venc, VENC_HS_INT_START_STOP_X);
|
|
DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
|
|
DUMPREG(venc, VENC_VS_INT_START_X);
|
|
DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
|
|
DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
|
|
DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
|
|
DUMPREG(venc, VENC_VS_EXT_STOP_Y);
|
|
DUMPREG(venc, VENC_AVID_START_STOP_X);
|
|
DUMPREG(venc, VENC_AVID_START_STOP_Y);
|
|
DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
|
|
DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
|
|
DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
|
|
DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
|
|
DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
|
|
DUMPREG(venc, VENC_GEN_CTRL);
|
|
DUMPREG(venc, VENC_OUTPUT_CONTROL);
|
|
DUMPREG(venc, VENC_OUTPUT_TEST);
|
|
|
|
venc_runtime_put(venc);
|
|
|
|
#undef DUMPREG
|
|
return 0;
|
|
}
|
|
|
|
static int venc_get_clocks(struct venc_device *venc)
|
|
{
|
|
struct clk *clk;
|
|
|
|
if (venc->requires_tv_dac_clk) {
|
|
clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
|
|
if (IS_ERR(clk)) {
|
|
DSSERR("can't get tv_dac_clk\n");
|
|
return PTR_ERR(clk);
|
|
}
|
|
} else {
|
|
clk = NULL;
|
|
}
|
|
|
|
venc->tv_dac_clk = clk;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int venc_connect(struct omap_dss_device *src,
|
|
struct omap_dss_device *dst)
|
|
{
|
|
int r;
|
|
|
|
r = omapdss_device_connect(dst->dss, dst, dst->next);
|
|
if (r)
|
|
return r;
|
|
|
|
dst->dispc_channel_connected = true;
|
|
return 0;
|
|
}
|
|
|
|
static void venc_disconnect(struct omap_dss_device *src,
|
|
struct omap_dss_device *dst)
|
|
{
|
|
dst->dispc_channel_connected = false;
|
|
|
|
omapdss_device_disconnect(dst, dst->next);
|
|
}
|
|
|
|
static const struct omap_dss_device_ops venc_ops = {
|
|
.connect = venc_connect,
|
|
.disconnect = venc_disconnect,
|
|
|
|
.enable = venc_display_enable,
|
|
.disable = venc_display_disable,
|
|
|
|
.check_timings = venc_check_timings,
|
|
.get_timings = venc_get_timings,
|
|
.set_timings = venc_set_timings,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Component Bind & Unbind
|
|
*/
|
|
|
|
static int venc_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct dss_device *dss = dss_get_device(master);
|
|
struct venc_device *venc = dev_get_drvdata(dev);
|
|
u8 rev_id;
|
|
int r;
|
|
|
|
venc->dss = dss;
|
|
|
|
r = venc_runtime_get(venc);
|
|
if (r)
|
|
return r;
|
|
|
|
rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
|
|
dev_dbg(dev, "OMAP VENC rev %d\n", rev_id);
|
|
|
|
venc_runtime_put(venc);
|
|
|
|
venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
|
|
venc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void venc_unbind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct venc_device *venc = dev_get_drvdata(dev);
|
|
|
|
dss_debugfs_remove_file(venc->debugfs);
|
|
}
|
|
|
|
static const struct component_ops venc_component_ops = {
|
|
.bind = venc_bind,
|
|
.unbind = venc_unbind,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Probe & Remove, Suspend & Resume
|
|
*/
|
|
|
|
static int venc_init_output(struct venc_device *venc)
|
|
{
|
|
struct omap_dss_device *out = &venc->output;
|
|
int r;
|
|
|
|
out->dev = &venc->pdev->dev;
|
|
out->id = OMAP_DSS_OUTPUT_VENC;
|
|
out->output_type = OMAP_DISPLAY_TYPE_VENC;
|
|
out->name = "venc.0";
|
|
out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
|
|
out->ops = &venc_ops;
|
|
out->owner = THIS_MODULE;
|
|
out->of_ports = BIT(0);
|
|
|
|
out->next = omapdss_of_find_connected_device(out->dev->of_node, 0);
|
|
if (IS_ERR(out->next)) {
|
|
if (PTR_ERR(out->next) != -EPROBE_DEFER)
|
|
dev_err(out->dev, "failed to find video sink\n");
|
|
return PTR_ERR(out->next);
|
|
}
|
|
|
|
r = omapdss_output_validate(out);
|
|
if (r) {
|
|
omapdss_device_put(out->next);
|
|
out->next = NULL;
|
|
return r;
|
|
}
|
|
|
|
omapdss_device_register(out);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void venc_uninit_output(struct venc_device *venc)
|
|
{
|
|
if (venc->output.next)
|
|
omapdss_device_put(venc->output.next);
|
|
omapdss_device_unregister(&venc->output);
|
|
}
|
|
|
|
static int venc_probe_of(struct venc_device *venc)
|
|
{
|
|
struct device_node *node = venc->pdev->dev.of_node;
|
|
struct device_node *ep;
|
|
u32 channels;
|
|
int r;
|
|
|
|
ep = of_graph_get_endpoint_by_regs(node, 0, 0);
|
|
if (!ep)
|
|
return 0;
|
|
|
|
venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
|
|
|
|
r = of_property_read_u32(ep, "ti,channels", &channels);
|
|
if (r) {
|
|
dev_err(&venc->pdev->dev,
|
|
"failed to read property 'ti,channels': %d\n", r);
|
|
goto err;
|
|
}
|
|
|
|
switch (channels) {
|
|
case 1:
|
|
venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
|
|
break;
|
|
case 2:
|
|
venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
|
|
break;
|
|
default:
|
|
dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
|
|
channels);
|
|
r = -EINVAL;
|
|
goto err;
|
|
}
|
|
|
|
of_node_put(ep);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
of_node_put(ep);
|
|
return r;
|
|
}
|
|
|
|
static const struct soc_device_attribute venc_soc_devices[] = {
|
|
{ .machine = "OMAP3[45]*" },
|
|
{ .machine = "AM35*" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static int venc_probe(struct platform_device *pdev)
|
|
{
|
|
struct venc_device *venc;
|
|
struct resource *venc_mem;
|
|
int r;
|
|
|
|
venc = kzalloc(sizeof(*venc), GFP_KERNEL);
|
|
if (!venc)
|
|
return -ENOMEM;
|
|
|
|
venc->pdev = pdev;
|
|
|
|
platform_set_drvdata(pdev, venc);
|
|
|
|
/* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
|
|
if (soc_device_match(venc_soc_devices))
|
|
venc->requires_tv_dac_clk = true;
|
|
|
|
mutex_init(&venc->venc_lock);
|
|
|
|
venc->wss_data = 0;
|
|
venc->vm = omap_dss_pal_vm;
|
|
|
|
venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
|
|
venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
|
|
if (IS_ERR(venc->base)) {
|
|
r = PTR_ERR(venc->base);
|
|
goto err_free;
|
|
}
|
|
|
|
venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda");
|
|
if (IS_ERR(venc->vdda_dac_reg)) {
|
|
r = PTR_ERR(venc->vdda_dac_reg);
|
|
if (r != -EPROBE_DEFER)
|
|
DSSERR("can't get VDDA_DAC regulator\n");
|
|
goto err_free;
|
|
}
|
|
|
|
r = venc_get_clocks(venc);
|
|
if (r)
|
|
goto err_free;
|
|
|
|
r = venc_probe_of(venc);
|
|
if (r)
|
|
goto err_free;
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
r = venc_init_output(venc);
|
|
if (r)
|
|
goto err_pm_disable;
|
|
|
|
r = component_add(&pdev->dev, &venc_component_ops);
|
|
if (r)
|
|
goto err_uninit_output;
|
|
|
|
return 0;
|
|
|
|
err_uninit_output:
|
|
venc_uninit_output(venc);
|
|
err_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
err_free:
|
|
kfree(venc);
|
|
return r;
|
|
}
|
|
|
|
static int venc_remove(struct platform_device *pdev)
|
|
{
|
|
struct venc_device *venc = platform_get_drvdata(pdev);
|
|
|
|
component_del(&pdev->dev, &venc_component_ops);
|
|
|
|
venc_uninit_output(venc);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
kfree(venc);
|
|
return 0;
|
|
}
|
|
|
|
static int venc_runtime_suspend(struct device *dev)
|
|
{
|
|
struct venc_device *venc = dev_get_drvdata(dev);
|
|
|
|
if (venc->tv_dac_clk)
|
|
clk_disable_unprepare(venc->tv_dac_clk);
|
|
|
|
dispc_runtime_put(venc->dss->dispc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int venc_runtime_resume(struct device *dev)
|
|
{
|
|
struct venc_device *venc = dev_get_drvdata(dev);
|
|
int r;
|
|
|
|
r = dispc_runtime_get(venc->dss->dispc);
|
|
if (r < 0)
|
|
return r;
|
|
|
|
if (venc->tv_dac_clk)
|
|
clk_prepare_enable(venc->tv_dac_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops venc_pm_ops = {
|
|
.runtime_suspend = venc_runtime_suspend,
|
|
.runtime_resume = venc_runtime_resume,
|
|
};
|
|
|
|
static const struct of_device_id venc_of_match[] = {
|
|
{ .compatible = "ti,omap2-venc", },
|
|
{ .compatible = "ti,omap3-venc", },
|
|
{ .compatible = "ti,omap4-venc", },
|
|
{},
|
|
};
|
|
|
|
struct platform_driver omap_venchw_driver = {
|
|
.probe = venc_probe,
|
|
.remove = venc_remove,
|
|
.driver = {
|
|
.name = "omapdss_venc",
|
|
.pm = &venc_pm_ops,
|
|
.of_match_table = venc_of_match,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
};
|