37e91bd4b3
When a PASID is used for SVA by the device, it's possible that the PASID
entry is cleared before the device flushes all ongoing DMA requests. The
IOMMU should tolerate and ignore the non-recoverable faults caused by the
untranslated requests from this device.
For example, when an exception happens, the process terminates before the
device driver stops DMA and call IOMMU driver to unbind PASID. The flow
of process exist is as follows:
do_exit() {
exit_mm() {
mm_put();
exit_mmap() {
intel_invalidate_range() //mmu notifier
tlb_finish_mmu()
mmu_notifier_release(mm) {
intel_iommu_release() {
[2] intel_iommu_teardown_pasid();
intel_iommu_flush_tlbs();
}
}
unmap_vmas();
free_pgtables();
};
}
exit_files(tsk) {
close_files() {
dsa_close();
[1] dsa_stop_dma();
intel_svm_unbind_pasid();
}
}
}
Care must be taken on VT-d to avoid unrecoverable faults between the time
window of [1] and [2]. [Process exist flow was contributed by Jacob Pan.]
Intel VT-d provides such function through the FPD bit of the PASID entry.
This sets FPD bit when PASID entry is changing from present to nonpresent
in the mm notifier and will clear it when the pasid is unbound.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Link: https://lore.kernel.org/r/20200516062101.29541-15-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
129 lines
4.1 KiB
C
129 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* intel-pasid.h - PASID idr, table and entry header
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*
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* Copyright (C) 2018 Intel Corporation
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*
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* Author: Lu Baolu <baolu.lu@linux.intel.com>
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*/
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#ifndef __INTEL_PASID_H
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#define __INTEL_PASID_H
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#define PASID_RID2PASID 0x0
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#define PASID_MIN 0x1
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#define PASID_MAX 0x100000
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#define PASID_PTE_MASK 0x3F
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#define PASID_PTE_PRESENT 1
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#define PASID_PTE_FPD 2
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#define PDE_PFN_MASK PAGE_MASK
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#define PASID_PDE_SHIFT 6
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#define MAX_NR_PASID_BITS 20
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#define PASID_TBL_ENTRIES BIT(PASID_PDE_SHIFT)
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#define is_pasid_enabled(entry) (((entry)->lo >> 3) & 0x1)
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#define get_pasid_dir_size(entry) (1 << ((((entry)->lo >> 9) & 0x7) + 7))
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/* Virtual command interface for enlightened pasid management. */
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#define VCMD_CMD_ALLOC 0x1
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#define VCMD_CMD_FREE 0x2
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#define VCMD_VRSP_IP 0x1
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#define VCMD_VRSP_SC(e) (((e) >> 1) & 0x3)
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#define VCMD_VRSP_SC_SUCCESS 0
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#define VCMD_VRSP_SC_NO_PASID_AVAIL 1
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#define VCMD_VRSP_SC_INVALID_PASID 1
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#define VCMD_VRSP_RESULT_PASID(e) (((e) >> 8) & 0xfffff)
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#define VCMD_CMD_OPERAND(e) ((e) << 8)
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/*
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* Domain ID reserved for pasid entries programmed for first-level
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* only and pass-through transfer modes.
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*/
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#define FLPT_DEFAULT_DID 1
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/*
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* The SUPERVISOR_MODE flag indicates a first level translation which
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* can be used for access to kernel addresses. It is valid only for
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* access to the kernel's static 1:1 mapping of physical memory — not
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* to vmalloc or even module mappings.
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*/
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#define PASID_FLAG_SUPERVISOR_MODE BIT(0)
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#define PASID_FLAG_NESTED BIT(1)
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/*
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* The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-
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* level translation, otherwise, 4-level paging will be used.
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*/
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#define PASID_FLAG_FL5LP BIT(1)
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struct pasid_dir_entry {
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u64 val;
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};
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struct pasid_entry {
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u64 val[8];
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};
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#define PASID_ENTRY_PGTT_FL_ONLY (1)
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#define PASID_ENTRY_PGTT_SL_ONLY (2)
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#define PASID_ENTRY_PGTT_NESTED (3)
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#define PASID_ENTRY_PGTT_PT (4)
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/* The representative of a PASID table */
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struct pasid_table {
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void *table; /* pasid table pointer */
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int order; /* page order of pasid table */
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int max_pasid; /* max pasid */
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struct list_head dev; /* device list */
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};
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/* Get PRESENT bit of a PASID directory entry. */
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static inline bool pasid_pde_is_present(struct pasid_dir_entry *pde)
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{
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return READ_ONCE(pde->val) & PASID_PTE_PRESENT;
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}
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/* Get PASID table from a PASID directory entry. */
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static inline struct pasid_entry *
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get_pasid_table_from_pde(struct pasid_dir_entry *pde)
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{
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if (!pasid_pde_is_present(pde))
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return NULL;
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return phys_to_virt(READ_ONCE(pde->val) & PDE_PFN_MASK);
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}
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/* Get PRESENT bit of a PASID table entry. */
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static inline bool pasid_pte_is_present(struct pasid_entry *pte)
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{
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return READ_ONCE(pte->val[0]) & PASID_PTE_PRESENT;
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}
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extern u32 intel_pasid_max_id;
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int intel_pasid_alloc_id(void *ptr, int start, int end, gfp_t gfp);
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void intel_pasid_free_id(int pasid);
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void *intel_pasid_lookup_id(int pasid);
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int intel_pasid_alloc_table(struct device *dev);
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void intel_pasid_free_table(struct device *dev);
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struct pasid_table *intel_pasid_get_table(struct device *dev);
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int intel_pasid_get_dev_max_id(struct device *dev);
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struct pasid_entry *intel_pasid_get_entry(struct device *dev, int pasid);
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int intel_pasid_setup_first_level(struct intel_iommu *iommu,
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struct device *dev, pgd_t *pgd,
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int pasid, u16 did, int flags);
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int intel_pasid_setup_second_level(struct intel_iommu *iommu,
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struct dmar_domain *domain,
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struct device *dev, int pasid);
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int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
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struct dmar_domain *domain,
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struct device *dev, int pasid);
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int intel_pasid_setup_nested(struct intel_iommu *iommu,
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struct device *dev, pgd_t *pgd, int pasid,
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struct iommu_gpasid_bind_data_vtd *pasid_data,
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struct dmar_domain *domain, int addr_width);
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void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
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struct device *dev, int pasid,
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bool fault_ignore);
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int vcmd_alloc_pasid(struct intel_iommu *iommu, unsigned int *pasid);
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void vcmd_free_pasid(struct intel_iommu *iommu, unsigned int pasid);
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#endif /* __INTEL_PASID_H */
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