d1d47ec6e6
Recent U-Boot commit 5ccd29c3679b3669b0bde5c501c1aa0f325a7acb caused the "cpu-release-addr" device tree property to contain the physical RAM location that secondary cores were spinning at. Previously, the "cpu-release-addr" property contained a value referencing the boot page translation address range of 0xfffffxxx, which then indirectly accessed RAM. The "cpu-release-addr" is currently ioremapped and the secondary cores kicked. However, due to the recent change in "cpu-release-addr", it sometimes points to a memory location in low memory that cannot be ioremapped. For example on a P2020-based board with 512MB of RAM the following error occurs on bootup: <...> mpic: requesting IPIs ... __ioremap(): phys addr 0x1ffff000 is RAM lr c05df9a0 Unable to handle kernel paging request for data at address 0x00000014 Faulting instruction address: 0xc05df9b0 Oops: Kernel access of bad area, sig: 11 [#1] SMP NR_CPUS=2 P2020 RDB Modules linked in: <... eventual kernel panic> Adding logic to conditionally ioremap or access memory directly resolves the issue. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Nate Case <ncase@xes-inc.com> Reported-by: Dipen Dudhat <B09055@freescale.com> Tested-by: Dipen Dudhat <B09055@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
126 lines
3 KiB
C
126 lines
3 KiB
C
/*
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* Author: Andy Fleming <afleming@freescale.com>
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* Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2006-2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <asm/machdep.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/mpic.h>
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#include <asm/cacheflush.h>
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#include <asm/dbell.h>
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#include <sysdev/fsl_soc.h>
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extern void __early_start(void);
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#define BOOT_ENTRY_ADDR_UPPER 0
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#define BOOT_ENTRY_ADDR_LOWER 1
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#define BOOT_ENTRY_R3_UPPER 2
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#define BOOT_ENTRY_R3_LOWER 3
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#define BOOT_ENTRY_RESV 4
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#define BOOT_ENTRY_PIR 5
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#define BOOT_ENTRY_R6_UPPER 6
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#define BOOT_ENTRY_R6_LOWER 7
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#define NUM_BOOT_ENTRY 8
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#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
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static void __init
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smp_85xx_kick_cpu(int nr)
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{
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unsigned long flags;
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const u64 *cpu_rel_addr;
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__iomem u32 *bptr_vaddr;
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struct device_node *np;
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int n = 0;
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int ioremappable;
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WARN_ON (nr < 0 || nr >= NR_CPUS);
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pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr);
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np = of_get_cpu_node(nr, NULL);
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cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
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if (cpu_rel_addr == NULL) {
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printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr);
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return;
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}
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/*
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* A secondary core could be in a spinloop in the bootpage
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* (0xfffff000), somewhere in highmem, or somewhere in lowmem.
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* The bootpage and highmem can be accessed via ioremap(), but
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* we need to directly access the spinloop if its in lowmem.
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*/
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ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
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/* Map the spin table */
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if (ioremappable)
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bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);
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else
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bptr_vaddr = phys_to_virt(*cpu_rel_addr);
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local_irq_save(flags);
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out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr);
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out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start));
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if (!ioremappable)
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flush_dcache_range((ulong)bptr_vaddr,
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(ulong)(bptr_vaddr + SIZE_BOOT_ENTRY));
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/* Wait a bit for the CPU to ack. */
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while ((__secondary_hold_acknowledge != nr) && (++n < 1000))
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mdelay(1);
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local_irq_restore(flags);
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if (ioremappable)
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iounmap(bptr_vaddr);
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pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
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}
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static void __init
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smp_85xx_setup_cpu(int cpu_nr)
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{
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mpic_setup_this_cpu();
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}
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struct smp_ops_t smp_85xx_ops = {
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.kick_cpu = smp_85xx_kick_cpu,
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};
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void __init mpc85xx_smp_init(void)
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{
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struct device_node *np;
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np = of_find_node_by_type(NULL, "open-pic");
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if (np) {
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smp_85xx_ops.probe = smp_mpic_probe;
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smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
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smp_85xx_ops.message_pass = smp_mpic_message_pass;
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}
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if (cpu_has_feature(CPU_FTR_DBELL))
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smp_85xx_ops.message_pass = smp_dbell_message_pass;
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BUG_ON(!smp_85xx_ops.message_pass);
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smp_ops = &smp_85xx_ops;
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}
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