![Stafford Horne](/assets/img/avatar_default.png)
In case timers are not in sync when cpus start (i.e. hot plug / offset resets) we need to synchronize the secondary cpus internal timer with the main cpu. This is needed as in OpenRISC SMP there is only one clocksource registered which reads from the same ttcr register on each cpu. This synchronization routine heavily borrows from mips implementation that does something similar. Signed-off-by: Stafford Horne <shorne@gmail.com>
24 lines
627 B
C
24 lines
627 B
C
/*
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* OpenRISC timer API
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*
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* Copyright (C) 2017 by Stafford Horne (shorne@gmail.com)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_OR1K_TIME_H
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#define __ASM_OR1K_TIME_H
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extern void openrisc_clockevent_init(void);
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extern void openrisc_timer_set(unsigned long count);
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extern void openrisc_timer_set_next(unsigned long delta);
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#ifdef CONFIG_SMP
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extern void synchronise_count_master(int cpu);
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extern void synchronise_count_slave(int cpu);
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#endif
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#endif /* __ASM_OR1K_TIME_H */
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