![Sebastian Ott](/assets/img/avatar_default.png)
In a virtualized setup lazy flushing can lead to the hypervisor running out of resources when lots of guest pages need to be pinned. In this situation simply trigger a global flush to give the hypervisor a chance to free some of these resources. Signed-off-by: Sebastian Ott <sebott@linux.vnet.ibm.com> Reviewed-by: Gerald Schaefer <gerald.schaefer@de.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
234 lines
4.5 KiB
C
234 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* s390 specific pci instructions
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*
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* Copyright IBM Corp. 2013
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*/
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#include <linux/export.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <asm/facility.h>
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#include <asm/pci_insn.h>
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#include <asm/pci_debug.h>
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#include <asm/processor.h>
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#define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
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static inline void zpci_err_insn(u8 cc, u8 status, u64 req, u64 offset)
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{
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struct {
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u64 req;
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u64 offset;
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u8 cc;
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u8 status;
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} __packed data = {req, offset, cc, status};
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zpci_err_hex(&data, sizeof(data));
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}
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/* Modify PCI Function Controls */
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static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
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{
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u8 cc;
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asm volatile (
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" .insn rxy,0xe300000000d0,%[req],%[fib]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
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: : "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
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{
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u8 cc;
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do {
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cc = __mpcifc(req, fib, status);
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if (cc == 2)
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msleep(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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zpci_err_insn(cc, *status, req, 0);
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return cc;
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}
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/* Refresh PCI Translations */
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static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
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{
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register u64 __addr asm("2") = addr;
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register u64 __range asm("3") = range;
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d30000,%[fn],%[addr]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn)
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: [addr] "d" (__addr), "d" (__range)
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: "cc");
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*status = fn >> 24 & 0xff;
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return cc;
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}
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int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
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{
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u8 cc, status;
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do {
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cc = __rpcit(fn, addr, range, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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zpci_err_insn(cc, status, addr, range);
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if (cc == 1 && (status == 4 || status == 16))
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return -ENOMEM;
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return (cc) ? -EIO : 0;
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}
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/* Set Interruption Controls */
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int zpci_set_irq_ctrl(u16 ctl, char *unused, u8 isc)
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{
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if (!test_facility(72))
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return -EIO;
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asm volatile (
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" .insn rsy,0xeb00000000d1,%[ctl],%[isc],%[u]\n"
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: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [u] "Q" (*unused));
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return 0;
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}
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/* PCI Load */
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static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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int cc = -ENXIO;
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u64 __data;
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asm volatile (
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" .insn rre,0xb9d20000,%[data],%[req]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [data] "=d" (__data), [req] "+d" (__req)
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: "d" (__offset)
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: "cc");
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*status = __req >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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u64 __data;
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int cc;
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cc = ____pcilg(&__data, req, offset, status);
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if (!cc)
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*data = __data;
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return cc;
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}
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int zpci_load(u64 *data, u64 req, u64 offset)
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{
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u8 status;
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int cc;
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do {
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cc = __pcilg(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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zpci_err_insn(cc, status, req, offset);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(zpci_load);
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/* PCI Store */
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static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
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{
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register u64 __req asm("2") = req;
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register u64 __offset asm("3") = offset;
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int cc = -ENXIO;
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asm volatile (
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" .insn rre,0xb9d00000,%[data],%[req]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [req] "+d" (__req)
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: "d" (__offset), [data] "d" (data)
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: "cc");
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*status = __req >> 24 & 0xff;
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return cc;
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}
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int zpci_store(u64 data, u64 req, u64 offset)
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{
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u8 status;
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int cc;
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do {
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cc = __pcistg(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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zpci_err_insn(cc, status, req, offset);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(zpci_store);
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/* PCI Store Block */
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static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
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{
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int cc = -ENXIO;
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asm volatile (
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" .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [req] "+d" (req)
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: [offset] "d" (offset), [data] "Q" (*data)
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: "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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int zpci_store_block(const u64 *data, u64 req, u64 offset)
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{
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u8 status;
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int cc;
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do {
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cc = __pcistb(data, req, offset, &status);
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if (cc == 2)
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udelay(ZPCI_INSN_BUSY_DELAY);
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} while (cc == 2);
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if (cc)
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zpci_err_insn(cc, status, req, offset);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(zpci_store_block);
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