62e59c4e69
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc. Found with this grep: git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>' I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
125 lines
3.1 KiB
C
125 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/A1 Core CPG Clocks
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*
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* Copyright (C) 2013 Ideas On Board SPRL
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* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/renesas.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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struct rz_cpg {
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struct clk_onecell_data data;
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void __iomem *reg;
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};
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#define CPG_FRQCR 0x10
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#define CPG_FRQCR2 0x14
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#define PPR0 0xFCFE3200
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#define PIBC0 0xFCFE7000
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#define MD_CLK(x) ((x >> 2) & 1) /* P0_2 */
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/* -----------------------------------------------------------------------------
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* Initialization
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*/
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static u16 __init rz_cpg_read_mode_pins(void)
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{
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void __iomem *ppr0, *pibc0;
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u16 modes;
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ppr0 = ioremap_nocache(PPR0, 2);
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pibc0 = ioremap_nocache(PIBC0, 2);
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BUG_ON(!ppr0 || !pibc0);
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iowrite16(4, pibc0); /* enable input buffer */
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modes = ioread16(ppr0);
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iounmap(ppr0);
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iounmap(pibc0);
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return modes;
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}
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static struct clk * __init
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rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
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{
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u32 val;
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unsigned mult;
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static const unsigned frqcr_tab[4] = { 3, 2, 0, 1 };
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if (strcmp(name, "pll") == 0) {
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unsigned int cpg_mode = MD_CLK(rz_cpg_read_mode_pins());
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const char *parent_name = of_clk_get_parent_name(np, cpg_mode);
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mult = cpg_mode ? (32 / 4) : 30;
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return clk_register_fixed_factor(NULL, name, parent_name, 0, mult, 1);
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}
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/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
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if (!cpg->reg)
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return ERR_PTR(-ENXIO);
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/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
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* and the constraint that always g <= i. To get the rz platform started,
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* let them run at fixed current speed and implement the details later.
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*/
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if (strcmp(name, "i") == 0)
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val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
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else if (strcmp(name, "g") == 0)
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val = readl(cpg->reg + CPG_FRQCR2) & 3;
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else
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return ERR_PTR(-EINVAL);
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mult = frqcr_tab[val];
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return clk_register_fixed_factor(NULL, name, "pll", 0, mult, 3);
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}
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static void __init rz_cpg_clocks_init(struct device_node *np)
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{
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struct rz_cpg *cpg;
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struct clk **clks;
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unsigned i;
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int num_clks;
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num_clks = of_property_count_strings(np, "clock-output-names");
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if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
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return;
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cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
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clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
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BUG_ON(!cpg || !clks);
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cpg->data.clks = clks;
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cpg->data.clk_num = num_clks;
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cpg->reg = of_iomap(np, 0);
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for (i = 0; i < num_clks; ++i) {
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const char *name;
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struct clk *clk;
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of_property_read_string_index(np, "clock-output-names", i, &name);
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clk = rz_cpg_register_clock(np, cpg, name);
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if (IS_ERR(clk))
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pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
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__func__, np, name, PTR_ERR(clk));
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else
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cpg->data.clks[i] = clk;
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}
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
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cpg_mstp_add_clk_domain(np);
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}
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CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
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