![Anson Huang](/assets/img/avatar_default.png)
No need to initialize flags as 0, remove the initialization. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
192 lines
4.4 KiB
C
192 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2018 NXP
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*/
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#include <linux/clk-provider.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define PCG_PREDIV_SHIFT 16
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#define PCG_PREDIV_WIDTH 3
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#define PCG_PREDIV_MAX 8
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#define PCG_DIV_SHIFT 0
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#define PCG_CORE_DIV_WIDTH 3
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#define PCG_DIV_WIDTH 6
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#define PCG_DIV_MAX 64
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#define PCG_PCS_SHIFT 24
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#define PCG_PCS_MASK 0x7
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#define PCG_CGC_SHIFT 28
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static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned long prediv_rate;
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unsigned int prediv_value;
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unsigned int div_value;
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prediv_value = readl(divider->reg) >> divider->shift;
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prediv_value &= clk_div_mask(divider->width);
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prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
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NULL, divider->flags,
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divider->width);
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div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
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div_value &= clk_div_mask(PCG_DIV_WIDTH);
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return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
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divider->flags, PCG_DIV_WIDTH);
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}
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static int imx8m_clk_composite_compute_dividers(unsigned long rate,
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unsigned long parent_rate,
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int *prediv, int *postdiv)
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{
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int div1, div2;
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int error = INT_MAX;
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int ret = -EINVAL;
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*prediv = 1;
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*postdiv = 1;
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for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
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for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
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int new_error = ((parent_rate / div1) / div2) - rate;
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if (abs(new_error) < abs(error)) {
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*prediv = div1;
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*postdiv = div2;
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error = new_error;
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ret = 0;
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}
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}
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}
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return ret;
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}
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static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *prate)
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{
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int prediv_value;
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int div_value;
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imx8m_clk_composite_compute_dividers(rate, *prate,
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&prediv_value, &div_value);
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rate = DIV_ROUND_UP(*prate, prediv_value);
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return DIV_ROUND_UP(rate, div_value);
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}
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static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned long flags;
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int prediv_value;
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int div_value;
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int ret;
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u32 val;
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ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
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&prediv_value, &div_value);
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if (ret)
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return -EINVAL;
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spin_lock_irqsave(divider->lock, flags);
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val = readl(divider->reg);
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val &= ~((clk_div_mask(divider->width) << divider->shift) |
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(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
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val |= (u32)(prediv_value - 1) << divider->shift;
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val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
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writel(val, divider->reg);
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spin_unlock_irqrestore(divider->lock, flags);
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return ret;
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}
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static const struct clk_ops imx8m_clk_composite_divider_ops = {
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.recalc_rate = imx8m_clk_composite_divider_recalc_rate,
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.round_rate = imx8m_clk_composite_divider_round_rate,
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.set_rate = imx8m_clk_composite_divider_set_rate,
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};
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struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
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const char * const *parent_names,
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int num_parents, void __iomem *reg,
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u32 composite_flags,
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unsigned long flags)
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{
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struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
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struct clk_hw *div_hw, *gate_hw;
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struct clk_divider *div = NULL;
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struct clk_gate *gate = NULL;
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struct clk_mux *mux = NULL;
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const struct clk_ops *divider_ops;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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goto fail;
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mux_hw = &mux->hw;
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mux->reg = reg;
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mux->shift = PCG_PCS_SHIFT;
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mux->mask = PCG_PCS_MASK;
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mux->lock = &imx_ccm_lock;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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goto fail;
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div_hw = &div->hw;
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div->reg = reg;
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if (composite_flags & IMX_COMPOSITE_CORE) {
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div->shift = PCG_DIV_SHIFT;
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div->width = PCG_CORE_DIV_WIDTH;
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divider_ops = &clk_divider_ops;
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} else {
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div->shift = PCG_PREDIV_SHIFT;
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div->width = PCG_PREDIV_WIDTH;
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divider_ops = &imx8m_clk_composite_divider_ops;
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}
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div->lock = &imx_ccm_lock;
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div->flags = CLK_DIVIDER_ROUND_CLOSEST;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto fail;
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gate_hw = &gate->hw;
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gate->reg = reg;
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gate->bit_idx = PCG_CGC_SHIFT;
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gate->lock = &imx_ccm_lock;
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux_hw, &clk_mux_ops, div_hw,
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divider_ops, gate_hw, &clk_gate_ops, flags);
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if (IS_ERR(hw))
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goto fail;
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return hw;
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fail:
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kfree(gate);
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kfree(div);
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kfree(mux);
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return ERR_CAST(hw);
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}
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