![Peng Fan](/assets/img/avatar_default.png)
It is not good to use enable/disable for PLLv4 which needs time to lock, because enable/disable is expected to be able run in interrupt context. So use prepare/unprepare. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
240 lines
5 KiB
C
240 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017~2018 NXP
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*
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* Author: Dong Aisheng <aisheng.dong@nxp.com>
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/slab.h>
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#include "clk.h"
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/* PLL Control Status Register (xPLLCSR) */
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#define PLL_CSR_OFFSET 0x0
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#define PLL_VLD BIT(24)
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#define PLL_EN BIT(0)
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/* PLL Configuration Register (xPLLCFG) */
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#define PLL_CFG_OFFSET 0x08
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#define BP_PLL_MULT 16
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#define BM_PLL_MULT (0x7f << 16)
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/* PLL Numerator Register (xPLLNUM) */
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#define PLL_NUM_OFFSET 0x10
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/* PLL Denominator Register (xPLLDENOM) */
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#define PLL_DENOM_OFFSET 0x14
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#define MAX_MFD 0x3fffffff
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#define DEFAULT_MFD 1000000
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struct clk_pllv4 {
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struct clk_hw hw;
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void __iomem *base;
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};
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/* Valid PLL MULT Table */
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static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
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#define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
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#define LOCK_TIMEOUT_US USEC_PER_MSEC
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static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
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{
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u32 csr;
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return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
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csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
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}
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static int clk_pllv4_is_prepared(struct clk_hw *hw)
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{
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struct clk_pllv4 *pll = to_clk_pllv4(hw);
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if (readl_relaxed(pll->base) & PLL_EN)
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return 1;
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return 0;
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}
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static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pllv4 *pll = to_clk_pllv4(hw);
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u32 mult, mfn, mfd;
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u64 temp64;
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mult = readl_relaxed(pll->base + PLL_CFG_OFFSET);
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mult &= BM_PLL_MULT;
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mult >>= BP_PLL_MULT;
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mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
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mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
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temp64 = parent_rate;
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temp64 *= mfn;
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do_div(temp64, mfd);
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return (parent_rate * mult) + (u32)temp64;
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}
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static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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unsigned long round_rate, i;
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u32 mfn, mfd = DEFAULT_MFD;
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bool found = false;
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u64 temp64;
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for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
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round_rate = parent_rate * pllv4_mult_table[i];
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if (rate >= round_rate) {
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found = true;
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break;
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}
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}
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if (!found) {
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pr_warn("%s: unable to round rate %lu, parent rate %lu\n",
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clk_hw_get_name(hw), rate, parent_rate);
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return 0;
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}
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if (parent_rate <= MAX_MFD)
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mfd = parent_rate;
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temp64 = (u64)(rate - round_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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/*
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* NOTE: The value of numerator must always be configured to be
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* less than the value of the denominator. If we can't get a proper
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* pair of mfn/mfd, we simply return the round_rate without using
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* the frac part.
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*/
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if (mfn >= mfd)
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return round_rate;
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temp64 = (u64)parent_rate;
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temp64 *= mfn;
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do_div(temp64, mfd);
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return round_rate + (u32)temp64;
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}
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static bool clk_pllv4_is_valid_mult(unsigned int mult)
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{
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int i;
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/* check if mult is in valid MULT table */
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for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
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if (pllv4_mult_table[i] == mult)
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return true;
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}
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return false;
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}
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static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv4 *pll = to_clk_pllv4(hw);
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u32 val, mult, mfn, mfd = DEFAULT_MFD;
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u64 temp64;
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mult = rate / parent_rate;
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if (!clk_pllv4_is_valid_mult(mult))
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return -EINVAL;
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if (parent_rate <= MAX_MFD)
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mfd = parent_rate;
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temp64 = (u64)(rate - mult * parent_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
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val &= ~BM_PLL_MULT;
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val |= mult << BP_PLL_MULT;
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writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
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writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
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writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
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return 0;
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}
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static int clk_pllv4_prepare(struct clk_hw *hw)
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{
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u32 val;
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struct clk_pllv4 *pll = to_clk_pllv4(hw);
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val = readl_relaxed(pll->base);
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val |= PLL_EN;
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writel_relaxed(val, pll->base);
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return clk_pllv4_wait_lock(pll);
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}
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static void clk_pllv4_unprepare(struct clk_hw *hw)
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{
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u32 val;
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struct clk_pllv4 *pll = to_clk_pllv4(hw);
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val = readl_relaxed(pll->base);
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val &= ~PLL_EN;
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writel_relaxed(val, pll->base);
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}
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static const struct clk_ops clk_pllv4_ops = {
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.recalc_rate = clk_pllv4_recalc_rate,
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.round_rate = clk_pllv4_round_rate,
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.set_rate = clk_pllv4_set_rate,
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.prepare = clk_pllv4_prepare,
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.unprepare = clk_pllv4_unprepare,
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.is_prepared = clk_pllv4_is_prepared,
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};
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struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
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void __iomem *base)
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{
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struct clk_pllv4 *pll;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->base = base;
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init.name = name;
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init.ops = &clk_pllv4_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.flags = CLK_SET_RATE_GATE;
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pll->hw.init = &init;
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hw = &pll->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(pll);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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