![Leonard Crestez](/assets/img/avatar_default.png)
The imx SC api strongly assumes that messages are composed out of
4-bytes words but some of our message structs have odd sizeofs.
This produces many oopses with CONFIG_KASAN=y.
Fix by marking with __aligned(4).
Fixes: 666aed2d13
("clk: imx: scu: add set parent support")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Link: https://lkml.kernel.org/r/aad021e432b3062c142973d09b766656eec18fde.1582216144.git.leonard.crestez@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
390 lines
9.1 KiB
C
390 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <linux/arm-smccc.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include "clk-scu.h"
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#define IMX_SIP_CPUFREQ 0xC2000001
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#define IMX_SIP_SET_CPUFREQ 0x00
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static struct imx_sc_ipc *ccm_ipc_handle;
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/*
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* struct clk_scu - Description of one SCU clock
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* @hw: the common clk_hw
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* @rsrc_id: resource ID of this SCU clock
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* @clk_type: type of this clock resource
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*/
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struct clk_scu {
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struct clk_hw hw;
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u16 rsrc_id;
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u8 clk_type;
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};
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/*
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* struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
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* @hdr: SCU protocol header
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* @rate: rate to set
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* @resource: clock resource to set rate
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* @clk: clk type of this resource
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*
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* This structure describes the SCU protocol of clock rate set
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*/
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struct imx_sc_msg_req_set_clock_rate {
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struct imx_sc_rpc_msg hdr;
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__le32 rate;
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__le16 resource;
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u8 clk;
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} __packed __aligned(4);
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struct req_get_clock_rate {
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__le16 resource;
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u8 clk;
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} __packed __aligned(4);
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struct resp_get_clock_rate {
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__le32 rate;
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};
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/*
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* struct imx_sc_msg_get_clock_rate - clock get rate protocol
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* @hdr: SCU protocol header
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* @req: get rate request protocol
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* @resp: get rate response protocol
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*
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* This structure describes the SCU protocol of clock rate get
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*/
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struct imx_sc_msg_get_clock_rate {
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struct imx_sc_rpc_msg hdr;
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union {
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struct req_get_clock_rate req;
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struct resp_get_clock_rate resp;
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} data;
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};
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/*
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* struct imx_sc_msg_get_clock_parent - clock get parent protocol
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* @hdr: SCU protocol header
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* @req: get parent request protocol
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* @resp: get parent response protocol
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*
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* This structure describes the SCU protocol of clock get parent
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*/
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struct imx_sc_msg_get_clock_parent {
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struct imx_sc_rpc_msg hdr;
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union {
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struct req_get_clock_parent {
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__le16 resource;
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u8 clk;
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} __packed __aligned(4) req;
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struct resp_get_clock_parent {
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u8 parent;
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} resp;
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} data;
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};
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/*
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* struct imx_sc_msg_set_clock_parent - clock set parent protocol
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* @hdr: SCU protocol header
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* @req: set parent request protocol
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*
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* This structure describes the SCU protocol of clock set parent
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*/
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struct imx_sc_msg_set_clock_parent {
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struct imx_sc_rpc_msg hdr;
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__le16 resource;
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u8 clk;
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u8 parent;
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} __packed;
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/*
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* struct imx_sc_msg_req_clock_enable - clock gate protocol
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* @hdr: SCU protocol header
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* @resource: clock resource to gate
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* @clk: clk type of this resource
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* @enable: whether gate off the clock
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* @autog: HW auto gate enable
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*
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* This structure describes the SCU protocol of clock gate
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*/
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struct imx_sc_msg_req_clock_enable {
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struct imx_sc_rpc_msg hdr;
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__le16 resource;
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u8 clk;
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u8 enable;
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u8 autog;
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} __packed __aligned(4);
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static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
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{
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return container_of(hw, struct clk_scu, hw);
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}
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int imx_clk_scu_init(void)
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{
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return imx_scu_get_handle(&ccm_ipc_handle);
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}
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/*
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* clk_scu_recalc_rate - Get clock rate for a SCU clock
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* @hw: clock to get rate for
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* @parent_rate: parent rate provided by common clock framework, not used
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*
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* Gets the current clock rate of a SCU clock. Returns the current
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* clock rate, or zero in failure.
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*/
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static unsigned long clk_scu_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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struct imx_sc_msg_get_clock_rate msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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int ret;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_PM;
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hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE;
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hdr->size = 2;
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msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
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msg.data.req.clk = clk->clk_type;
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ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
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if (ret) {
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pr_err("%s: failed to get clock rate %d\n",
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clk_hw_get_name(hw), ret);
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return 0;
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}
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return le32_to_cpu(msg.data.resp.rate);
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}
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/*
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* clk_scu_round_rate - Round clock rate for a SCU clock
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* @hw: clock to round rate for
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* @rate: rate to round
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* @parent_rate: parent rate provided by common clock framework, not used
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*
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* Returns the current clock rate, or zero in failure.
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*/
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static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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/*
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* Assume we support all the requested rate and let the SCU firmware
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* to handle the left work
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*/
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return rate;
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}
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static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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struct arm_smccc_res res;
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unsigned long cluster_id;
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if (clk->rsrc_id == IMX_SC_R_A35)
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cluster_id = 0;
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else
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return -EINVAL;
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/* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */
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arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ,
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cluster_id, rate, 0, 0, 0, 0, &res);
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return 0;
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}
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/*
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* clk_scu_set_rate - Set rate for a SCU clock
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* @hw: clock to change rate for
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* @rate: target rate for the clock
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* @parent_rate: rate of the clock parent, not used for SCU clocks
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*
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* Sets a clock frequency for a SCU clock. Returns the SCU
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* protocol status.
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*/
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static int clk_scu_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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struct imx_sc_msg_req_set_clock_rate msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_PM;
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hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE;
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hdr->size = 3;
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msg.rate = cpu_to_le32(rate);
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msg.resource = cpu_to_le16(clk->rsrc_id);
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msg.clk = clk->clk_type;
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return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
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}
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static u8 clk_scu_get_parent(struct clk_hw *hw)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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struct imx_sc_msg_get_clock_parent msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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int ret;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_PM;
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hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT;
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hdr->size = 2;
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msg.data.req.resource = cpu_to_le16(clk->rsrc_id);
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msg.data.req.clk = clk->clk_type;
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ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
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if (ret) {
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pr_err("%s: failed to get clock parent %d\n",
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clk_hw_get_name(hw), ret);
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return 0;
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}
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return msg.data.resp.parent;
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}
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static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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struct imx_sc_msg_set_clock_parent msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_PM;
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hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT;
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hdr->size = 2;
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msg.resource = cpu_to_le16(clk->rsrc_id);
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msg.clk = clk->clk_type;
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msg.parent = index;
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return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
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}
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static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource,
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u8 clk, bool enable, bool autog)
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{
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struct imx_sc_msg_req_clock_enable msg;
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struct imx_sc_rpc_msg *hdr = &msg.hdr;
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hdr->ver = IMX_SC_RPC_VERSION;
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hdr->svc = IMX_SC_RPC_SVC_PM;
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hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE;
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hdr->size = 3;
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msg.resource = cpu_to_le16(resource);
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msg.clk = clk;
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msg.enable = enable;
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msg.autog = autog;
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return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
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}
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/*
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* clk_scu_prepare - Enable a SCU clock
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* @hw: clock to enable
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*
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* Enable the clock at the DSC slice level
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*/
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static int clk_scu_prepare(struct clk_hw *hw)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
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clk->clk_type, true, false);
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}
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/*
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* clk_scu_unprepare - Disable a SCU clock
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* @hw: clock to enable
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*
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* Disable the clock at the DSC slice level
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*/
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static void clk_scu_unprepare(struct clk_hw *hw)
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{
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struct clk_scu *clk = to_clk_scu(hw);
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int ret;
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ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id,
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clk->clk_type, false, false);
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if (ret)
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pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
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ret);
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}
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static const struct clk_ops clk_scu_ops = {
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.recalc_rate = clk_scu_recalc_rate,
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.round_rate = clk_scu_round_rate,
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.set_rate = clk_scu_set_rate,
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.get_parent = clk_scu_get_parent,
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.set_parent = clk_scu_set_parent,
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.prepare = clk_scu_prepare,
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.unprepare = clk_scu_unprepare,
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};
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static const struct clk_ops clk_scu_cpu_ops = {
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.recalc_rate = clk_scu_recalc_rate,
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.round_rate = clk_scu_round_rate,
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.set_rate = clk_scu_atf_set_cpu_rate,
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.prepare = clk_scu_prepare,
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.unprepare = clk_scu_unprepare,
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};
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struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
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int num_parents, u32 rsrc_id, u8 clk_type)
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{
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struct clk_init_data init;
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struct clk_scu *clk;
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struct clk_hw *hw;
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int ret;
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clk = kzalloc(sizeof(*clk), GFP_KERNEL);
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if (!clk)
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return ERR_PTR(-ENOMEM);
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clk->rsrc_id = rsrc_id;
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clk->clk_type = clk_type;
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init.name = name;
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init.ops = &clk_scu_ops;
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if (rsrc_id == IMX_SC_R_A35)
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init.ops = &clk_scu_cpu_ops;
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else
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init.ops = &clk_scu_ops;
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init.parent_names = parents;
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init.num_parents = num_parents;
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/*
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* Note on MX8, the clocks are tightly coupled with power domain
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* that once the power domain is off, the clock status may be
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* lost. So we make it NOCACHE to let user to retrieve the real
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* clock status from HW instead of using the possible invalid
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* cached rate.
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*/
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init.flags = CLK_GET_RATE_NOCACHE;
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clk->hw.init = &init;
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hw = &clk->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(clk);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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