acbeec3d37
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2, clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct PMC register access during clk_ops and these PMC register read and write access will not happen when PMC is in secure mode. Any direct PMC register access from non-secure world will not go through. All the PMC clocks are moved to Tegra PMC driver with PMC as a clock provider. This patch removes tegra_pmc_clk_init along with corresponding clk ids from Tegra clock driver. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
30 lines
1 KiB
Makefile
30 lines
1 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-y += clk.o
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obj-y += clk-audio-sync.o
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obj-y += clk-dfll.o
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obj-y += clk-divider.o
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obj-y += clk-periph.o
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obj-y += clk-periph-fixed.o
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obj-y += clk-periph-gate.o
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obj-y += clk-pll.o
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obj-y += clk-pll-out.o
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obj-y += clk-sdmmc-mux.o
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obj-y += clk-super.o
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obj-y += clk-tegra-audio.o
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obj-y += clk-tegra-periph.o
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obj-y += clk-tegra-fixed.o
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obj-y += clk-tegra-super-gen4.o
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obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20-emc.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra20-emc.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
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obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
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obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o
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obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
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obj-y += cvb.o
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obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
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obj-$(CONFIG_CLK_TEGRA_BPMP) += clk-bpmp.o
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obj-y += clk-utils.o
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