a99d744d8c
This patch implements DFLL suspend and resume operation. During system suspend entry, CPU clock will switch CPU to safe clock source of PLLP and disables DFLL clock output. DFLL driver suspend confirms DFLL disable state and errors out on being active. DFLL is re-initialized during the DFLL driver resume as it goes through complete reset during suspend entry. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
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* Copyright (C) 2013-2019 NVIDIA Corporation. All rights reserved.
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*
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* Aleksandr Frid <afrid@nvidia.com>
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* Paul Walmsley <pwalmsley@nvidia.com>
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*/
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#ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
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#define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/types.h>
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#include "cvb.h"
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/**
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* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
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* @dev: struct device * that holds the OPP table for the DFLL
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* @max_freq: maximum frequency supported on this SoC
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* @cvb: CPU frequency table for this SoC
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* @alignment: parameters of the regulator step and offset
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* @init_clock_trimmers: callback to initialize clock trimmers
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* @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
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* @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
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*/
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struct tegra_dfll_soc_data {
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struct device *dev;
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unsigned long max_freq;
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const struct cvb_table *cvb;
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struct rail_alignment alignment;
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void (*init_clock_trimmers)(void);
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void (*set_clock_trimmers_high)(void);
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void (*set_clock_trimmers_low)(void);
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};
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int tegra_dfll_register(struct platform_device *pdev,
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struct tegra_dfll_soc_data *soc);
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struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
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int tegra_dfll_runtime_suspend(struct device *dev);
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int tegra_dfll_runtime_resume(struct device *dev);
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int tegra_dfll_suspend(struct device *dev);
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int tegra_dfll_resume(struct device *dev);
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#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */
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