![Sowjanya Komatineni](/assets/img/avatar_default.png)
This patch implements restore_context support for clk-periph and clk-sdmmc-mux clock operations to restore clock parent and rates on system resume. During system suspend, core power goes off and looses the context of the Tegra clock controller registers. So on system resume, clocks parent and rate are restored back to the context before suspend based on cached data. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
224 lines
6.2 KiB
C
224 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/export.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include "clk.h"
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static u8 clk_periph_get_parent(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *mux_ops = periph->mux_ops;
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struct clk_hw *mux_hw = &periph->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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return mux_ops->get_parent(mux_hw);
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}
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static int clk_periph_set_parent(struct clk_hw *hw, u8 index)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *mux_ops = periph->mux_ops;
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struct clk_hw *mux_hw = &periph->mux.hw;
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__clk_hw_set_clk(mux_hw, hw);
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return mux_ops->set_parent(mux_hw, index);
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}
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static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *div_ops = periph->div_ops;
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struct clk_hw *div_hw = &periph->divider.hw;
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__clk_hw_set_clk(div_hw, hw);
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return div_ops->recalc_rate(div_hw, parent_rate);
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}
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static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *div_ops = periph->div_ops;
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struct clk_hw *div_hw = &periph->divider.hw;
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__clk_hw_set_clk(div_hw, hw);
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return div_ops->round_rate(div_hw, rate, prate);
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}
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static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *div_ops = periph->div_ops;
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struct clk_hw *div_hw = &periph->divider.hw;
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__clk_hw_set_clk(div_hw, hw);
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return div_ops->set_rate(div_hw, rate, parent_rate);
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}
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static int clk_periph_is_enabled(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *gate_ops = periph->gate_ops;
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struct clk_hw *gate_hw = &periph->gate.hw;
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__clk_hw_set_clk(gate_hw, hw);
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return gate_ops->is_enabled(gate_hw);
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}
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static int clk_periph_enable(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *gate_ops = periph->gate_ops;
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struct clk_hw *gate_hw = &periph->gate.hw;
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__clk_hw_set_clk(gate_hw, hw);
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return gate_ops->enable(gate_hw);
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}
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static void clk_periph_disable(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *gate_ops = periph->gate_ops;
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struct clk_hw *gate_hw = &periph->gate.hw;
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gate_ops->disable(gate_hw);
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}
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static void clk_periph_restore_context(struct clk_hw *hw)
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{
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struct tegra_clk_periph *periph = to_clk_periph(hw);
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const struct clk_ops *div_ops = periph->div_ops;
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struct clk_hw *div_hw = &periph->divider.hw;
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int parent_id;
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parent_id = clk_hw_get_parent_index(hw);
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if (WARN_ON(parent_id < 0))
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return;
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if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV))
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div_ops->restore_context(div_hw);
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clk_periph_set_parent(hw, parent_id);
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}
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const struct clk_ops tegra_clk_periph_ops = {
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.get_parent = clk_periph_get_parent,
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.set_parent = clk_periph_set_parent,
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.recalc_rate = clk_periph_recalc_rate,
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.round_rate = clk_periph_round_rate,
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.set_rate = clk_periph_set_rate,
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.is_enabled = clk_periph_is_enabled,
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.enable = clk_periph_enable,
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.disable = clk_periph_disable,
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.restore_context = clk_periph_restore_context,
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};
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static const struct clk_ops tegra_clk_periph_nodiv_ops = {
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.get_parent = clk_periph_get_parent,
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.set_parent = clk_periph_set_parent,
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.is_enabled = clk_periph_is_enabled,
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.enable = clk_periph_enable,
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.disable = clk_periph_disable,
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.restore_context = clk_periph_restore_context,
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};
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static const struct clk_ops tegra_clk_periph_no_gate_ops = {
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.get_parent = clk_periph_get_parent,
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.set_parent = clk_periph_set_parent,
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.recalc_rate = clk_periph_recalc_rate,
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.round_rate = clk_periph_round_rate,
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.set_rate = clk_periph_set_rate,
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.restore_context = clk_periph_restore_context,
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};
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static struct clk *_tegra_clk_register_periph(const char *name,
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const char * const *parent_names, int num_parents,
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struct tegra_clk_periph *periph,
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void __iomem *clk_base, u32 offset,
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unsigned long flags)
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{
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struct clk *clk;
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struct clk_init_data init;
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const struct tegra_clk_periph_regs *bank;
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bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);
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if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {
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flags |= CLK_SET_RATE_PARENT;
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init.ops = &tegra_clk_periph_nodiv_ops;
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} else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE)
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init.ops = &tegra_clk_periph_no_gate_ops;
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else
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init.ops = &tegra_clk_periph_ops;
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init.name = name;
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init.flags = flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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bank = get_reg_bank(periph->gate.clk_num);
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if (!bank)
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return ERR_PTR(-EINVAL);
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/* Data in .init is copied by clk_register(), so stack variable OK */
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periph->hw.init = &init;
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periph->magic = TEGRA_CLK_PERIPH_MAGIC;
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periph->mux.reg = clk_base + offset;
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periph->divider.reg = div ? (clk_base + offset) : NULL;
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periph->gate.clk_base = clk_base;
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periph->gate.regs = bank;
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periph->gate.enable_refcnt = periph_clk_enb_refcnt;
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clk = clk_register(NULL, &periph->hw);
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if (IS_ERR(clk))
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return clk;
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periph->mux.hw.clk = clk;
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periph->divider.hw.clk = div ? clk : NULL;
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periph->gate.hw.clk = clk;
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return clk;
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}
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struct clk *tegra_clk_register_periph(const char *name,
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const char * const *parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset, unsigned long flags)
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{
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return _tegra_clk_register_periph(name, parent_names, num_parents,
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periph, clk_base, offset, flags);
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}
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struct clk *tegra_clk_register_periph_nodiv(const char *name,
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const char * const *parent_names, int num_parents,
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struct tegra_clk_periph *periph, void __iomem *clk_base,
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u32 offset)
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{
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periph->gate.flags |= TEGRA_PERIPH_NO_DIV;
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return _tegra_clk_register_periph(name, parent_names, num_parents,
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periph, clk_base, offset, CLK_SET_RATE_PARENT);
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}
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struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
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struct tegra_periph_init_data *init)
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{
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return _tegra_clk_register_periph(init->name, init->p.parent_names,
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init->num_parents, &init->periph,
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clk_base, init->offset, init->flags);
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}
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