fa62228240
This patch implements save and restore of pllout context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the state of pllout is saved and on resume it is restored back to have pllout in same state as before suspend. pllout rate is saved and restore in clock divider so it will be at same rate as before suspend when pllout state is restored. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
121 lines
2.7 KiB
C
121 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include "clk.h"
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#define pll_out_enb(p) (BIT(p->enb_bit_idx))
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#define pll_out_rst(p) (BIT(p->rst_bit_idx))
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static int clk_pll_out_is_enabled(struct clk_hw *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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u32 val = readl_relaxed(pll_out->reg);
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int state;
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state = (val & pll_out_enb(pll_out)) ? 1 : 0;
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if (!(val & (pll_out_rst(pll_out))))
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state = 0;
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return state;
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}
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static int clk_pll_out_enable(struct clk_hw *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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unsigned long flags = 0;
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u32 val;
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if (pll_out->lock)
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spin_lock_irqsave(pll_out->lock, flags);
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val = readl_relaxed(pll_out->reg);
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val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
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writel_relaxed(val, pll_out->reg);
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udelay(2);
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if (pll_out->lock)
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spin_unlock_irqrestore(pll_out->lock, flags);
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return 0;
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}
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static void clk_pll_out_disable(struct clk_hw *hw)
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{
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struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
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unsigned long flags = 0;
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u32 val;
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if (pll_out->lock)
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spin_lock_irqsave(pll_out->lock, flags);
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val = readl_relaxed(pll_out->reg);
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val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
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writel_relaxed(val, pll_out->reg);
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udelay(2);
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if (pll_out->lock)
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spin_unlock_irqrestore(pll_out->lock, flags);
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}
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static void tegra_clk_pll_out_restore_context(struct clk_hw *hw)
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{
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if (!__clk_get_enable_count(hw->clk))
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clk_pll_out_disable(hw);
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else
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clk_pll_out_enable(hw);
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}
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const struct clk_ops tegra_clk_pll_out_ops = {
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.is_enabled = clk_pll_out_is_enabled,
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.enable = clk_pll_out_enable,
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.disable = clk_pll_out_disable,
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.restore_context = tegra_clk_pll_out_restore_context,
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};
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struct clk *tegra_clk_register_pll_out(const char *name,
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const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
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u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags,
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spinlock_t *lock)
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{
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struct tegra_clk_pll_out *pll_out;
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struct clk *clk;
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struct clk_init_data init;
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pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
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if (!pll_out)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &tegra_clk_pll_out_ops;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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init.flags = flags;
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pll_out->reg = reg;
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pll_out->enb_bit_idx = enb_bit_idx;
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pll_out->rst_bit_idx = rst_bit_idx;
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pll_out->flags = pll_out_flags;
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pll_out->lock = lock;
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/* Data in .init is copied by clk_register(), so stack variable OK */
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pll_out->hw.init = &init;
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clk = clk_register(NULL, &pll_out->hw);
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if (IS_ERR(clk))
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kfree(pll_out);
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return clk;
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}
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