![Sowjanya Komatineni](/assets/img/avatar_default.png)
This patch implements restore_context for clk_super_mux and clk_super. During system supend, core power goes off the and context of Tegra CAR registers is lost. So on system resume, context of super clock registers are restored to have them in same state as before suspend. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
275 lines
7.1 KiB
C
275 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include "clk.h"
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#define SUPER_STATE_IDLE 0
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#define SUPER_STATE_RUN 1
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#define SUPER_STATE_IRQ 2
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#define SUPER_STATE_FIQ 3
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#define SUPER_STATE_SHIFT 28
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#define SUPER_STATE_MASK ((BIT(SUPER_STATE_IDLE) | BIT(SUPER_STATE_RUN) | \
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BIT(SUPER_STATE_IRQ) | BIT(SUPER_STATE_FIQ)) \
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<< SUPER_STATE_SHIFT)
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#define SUPER_LP_DIV2_BYPASS (1 << 16)
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#define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
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#define super_state_to_src_shift(m, s) ((m->width * s))
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#define super_state_to_src_mask(m) (((1 << m->width) - 1))
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#define CCLK_SRC_PLLP_OUT0 4
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#define CCLK_SRC_PLLP_OUT4 5
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static u8 clk_super_get_parent(struct clk_hw *hw)
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{
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struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
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u32 val, state;
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u8 source, shift;
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val = readl_relaxed(mux->reg);
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state = val & SUPER_STATE_MASK;
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BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
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(state != super_state(SUPER_STATE_IDLE)));
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shift = (state == super_state(SUPER_STATE_IDLE)) ?
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super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
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super_state_to_src_shift(mux, SUPER_STATE_RUN);
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source = (val >> shift) & super_state_to_src_mask(mux);
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/*
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* If LP_DIV2_BYPASS is not set and PLLX is current parent then
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* PLLX/2 is the input source to CCLKLP.
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*/
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if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) &&
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(source == mux->pllx_index))
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source = mux->div2_index;
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return source;
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}
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static int clk_super_set_parent(struct clk_hw *hw, u8 index)
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{
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struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
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u32 val, state;
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int err = 0;
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u8 parent_index, shift;
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unsigned long flags = 0;
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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val = readl_relaxed(mux->reg);
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state = val & SUPER_STATE_MASK;
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BUG_ON((state != super_state(SUPER_STATE_RUN)) &&
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(state != super_state(SUPER_STATE_IDLE)));
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shift = (state == super_state(SUPER_STATE_IDLE)) ?
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super_state_to_src_shift(mux, SUPER_STATE_IDLE) :
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super_state_to_src_shift(mux, SUPER_STATE_RUN);
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/*
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* For LP mode super-clock switch between PLLX direct
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* and divided-by-2 outputs is allowed only when other
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* than PLLX clock source is current parent.
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*/
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if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) ||
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(index == mux->pllx_index))) {
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parent_index = clk_super_get_parent(hw);
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if ((parent_index == mux->div2_index) ||
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(parent_index == mux->pllx_index)) {
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err = -EINVAL;
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goto out;
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}
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val ^= SUPER_LP_DIV2_BYPASS;
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writel_relaxed(val, mux->reg);
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udelay(2);
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if (index == mux->div2_index)
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index = mux->pllx_index;
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}
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/* enable PLLP branches to CPU before selecting PLLP source */
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if ((mux->flags & TEGRA210_CPU_CLK) &&
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(index == CCLK_SRC_PLLP_OUT0 || index == CCLK_SRC_PLLP_OUT4))
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tegra_clk_set_pllp_out_cpu(true);
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val &= ~((super_state_to_src_mask(mux)) << shift);
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val |= (index & (super_state_to_src_mask(mux))) << shift;
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writel_relaxed(val, mux->reg);
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udelay(2);
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/* disable PLLP branches to CPU if not used */
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if ((mux->flags & TEGRA210_CPU_CLK) &&
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index != CCLK_SRC_PLLP_OUT0 && index != CCLK_SRC_PLLP_OUT4)
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tegra_clk_set_pllp_out_cpu(false);
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out:
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return err;
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}
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static void clk_super_mux_restore_context(struct clk_hw *hw)
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{
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int parent_id;
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parent_id = clk_hw_get_parent_index(hw);
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if (WARN_ON(parent_id < 0))
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return;
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clk_super_set_parent(hw, parent_id);
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}
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static const struct clk_ops tegra_clk_super_mux_ops = {
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.get_parent = clk_super_get_parent,
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.set_parent = clk_super_set_parent,
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.restore_context = clk_super_mux_restore_context,
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};
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static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
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struct clk_hw *div_hw = &super->frac_div.hw;
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__clk_hw_set_clk(div_hw, hw);
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return super->div_ops->round_rate(div_hw, rate, parent_rate);
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}
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static unsigned long clk_super_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
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struct clk_hw *div_hw = &super->frac_div.hw;
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__clk_hw_set_clk(div_hw, hw);
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return super->div_ops->recalc_rate(div_hw, parent_rate);
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}
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static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
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struct clk_hw *div_hw = &super->frac_div.hw;
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__clk_hw_set_clk(div_hw, hw);
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return super->div_ops->set_rate(div_hw, rate, parent_rate);
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}
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static void clk_super_restore_context(struct clk_hw *hw)
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{
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struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
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struct clk_hw *div_hw = &super->frac_div.hw;
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int parent_id;
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parent_id = clk_hw_get_parent_index(hw);
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if (WARN_ON(parent_id < 0))
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return;
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super->div_ops->restore_context(div_hw);
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clk_super_set_parent(hw, parent_id);
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}
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const struct clk_ops tegra_clk_super_ops = {
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.get_parent = clk_super_get_parent,
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.set_parent = clk_super_set_parent,
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.set_rate = clk_super_set_rate,
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.round_rate = clk_super_round_rate,
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.recalc_rate = clk_super_recalc_rate,
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.restore_context = clk_super_restore_context,
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};
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struct clk *tegra_clk_register_super_mux(const char *name,
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const char **parent_names, u8 num_parents,
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unsigned long flags, void __iomem *reg, u8 clk_super_flags,
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u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock)
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{
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struct tegra_clk_super_mux *super;
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struct clk *clk;
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struct clk_init_data init;
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super = kzalloc(sizeof(*super), GFP_KERNEL);
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if (!super)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &tegra_clk_super_mux_ops;
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init.flags = flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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super->reg = reg;
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super->pllx_index = pllx_index;
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super->div2_index = div2_index;
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super->lock = lock;
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super->width = width;
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super->flags = clk_super_flags;
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/* Data in .init is copied by clk_register(), so stack variable OK */
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super->hw.init = &init;
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clk = clk_register(NULL, &super->hw);
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if (IS_ERR(clk))
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kfree(super);
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return clk;
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}
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struct clk *tegra_clk_register_super_clk(const char *name,
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const char * const *parent_names, u8 num_parents,
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unsigned long flags, void __iomem *reg, u8 clk_super_flags,
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spinlock_t *lock)
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{
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struct tegra_clk_super_mux *super;
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struct clk *clk;
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struct clk_init_data init;
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super = kzalloc(sizeof(*super), GFP_KERNEL);
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if (!super)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &tegra_clk_super_ops;
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init.flags = flags;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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super->reg = reg;
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super->lock = lock;
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super->width = 4;
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super->flags = clk_super_flags;
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super->frac_div.reg = reg + 4;
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super->frac_div.shift = 16;
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super->frac_div.width = 8;
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super->frac_div.frac_width = 1;
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super->frac_div.lock = lock;
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super->div_ops = &tegra_clk_frac_div_ops;
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/* Data in .init is copied by clk_register(), so stack variable OK */
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super->hw.init = &init;
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clk = clk_register(NULL, &super->hw);
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if (IS_ERR(clk))
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kfree(super);
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return clk;
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}
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