![Dmitry Osipenko](/assets/img/avatar_default.png)
A proper External Memory Controller clock rounding and parent selection functionality is required by the EMC drivers, it is not available using the generic clock implementation because only the Memory Controller driver is aware of what clock rates are actually available for a particular device. EMC drivers will have to register a Tegra-specific CLK-API callback which will perform rounding of a requested rate. EMC clock users won't be able to request EMC clock by getting -EPROBE_DEFER until EMC driver is probed and the callback is set up. The functionality is somewhat similar to the clk-emc.c which serves Tegra124+ SoCs. The later HW generations support more parent clock sources and the HW configuration / integration with the EMC drivers differs a tad from the older gens, hence it's not really worth to try to squash everything into a single source file. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
294 lines
6.3 KiB
C
294 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Based on drivers/clk/tegra/clk-emc.c
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Dmitry Osipenko <digetx@gmail.com>
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* Copyright (C) 2019 GRATE-DRIVER project
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*/
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#define pr_fmt(fmt) "tegra-emc-clk: " fmt
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#include <linux/bits.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/tegra.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK GENMASK(7, 0)
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#define CLK_SOURCE_EMC_2X_CLK_SRC_MASK GENMASK(31, 30)
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#define CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT 30
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#define MC_EMC_SAME_FREQ BIT(16)
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#define USE_PLLM_UD BIT(29)
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#define EMC_SRC_PLL_M 0
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#define EMC_SRC_PLL_C 1
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#define EMC_SRC_PLL_P 2
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#define EMC_SRC_CLK_M 3
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static const char * const emc_parent_clk_names[] = {
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"pll_m", "pll_c", "pll_p", "clk_m",
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};
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struct tegra_clk_emc {
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struct clk_hw hw;
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void __iomem *reg;
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bool mc_same_freq;
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bool want_low_jitter;
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tegra20_clk_emc_round_cb *round_cb;
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void *cb_arg;
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};
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static inline struct tegra_clk_emc *to_tegra_clk_emc(struct clk_hw *hw)
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{
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return container_of(hw, struct tegra_clk_emc, hw);
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}
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static unsigned long emc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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u32 val, div;
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val = readl_relaxed(emc->reg);
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div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
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return DIV_ROUND_UP(parent_rate * 2, div + 2);
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}
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static u8 emc_get_parent(struct clk_hw *hw)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
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}
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static int emc_set_parent(struct clk_hw *hw, u8 index)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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u32 val, div;
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val = readl_relaxed(emc->reg);
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val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
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val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
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div = val & CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
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if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
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val |= USE_PLLM_UD;
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else
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val &= ~USE_PLLM_UD;
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if (emc->mc_same_freq)
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val |= MC_EMC_SAME_FREQ;
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else
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val &= ~MC_EMC_SAME_FREQ;
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writel_relaxed(val, emc->reg);
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fence_udelay(1, emc->reg);
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return 0;
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}
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static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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unsigned int index;
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u32 val, div;
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div = div_frac_get(rate, parent_rate, 8, 1, 0);
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val = readl_relaxed(emc->reg);
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val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
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val |= div;
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index = val >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
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if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
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val |= USE_PLLM_UD;
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else
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val &= ~USE_PLLM_UD;
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if (emc->mc_same_freq)
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val |= MC_EMC_SAME_FREQ;
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else
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val &= ~MC_EMC_SAME_FREQ;
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writel_relaxed(val, emc->reg);
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fence_udelay(1, emc->reg);
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return 0;
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}
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static int emc_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate,
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u8 index)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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u32 val, div;
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div = div_frac_get(rate, parent_rate, 8, 1, 0);
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val = readl_relaxed(emc->reg);
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val &= ~CLK_SOURCE_EMC_2X_CLK_SRC_MASK;
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val |= index << CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT;
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val &= ~CLK_SOURCE_EMC_2X_CLK_DIVISOR_MASK;
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val |= div;
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if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter)
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val |= USE_PLLM_UD;
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else
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val &= ~USE_PLLM_UD;
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if (emc->mc_same_freq)
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val |= MC_EMC_SAME_FREQ;
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else
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val &= ~MC_EMC_SAME_FREQ;
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writel_relaxed(val, emc->reg);
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fence_udelay(1, emc->reg);
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return 0;
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}
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static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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struct tegra_clk_emc *emc = to_tegra_clk_emc(hw);
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struct clk_hw *parent_hw;
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unsigned long divided_rate;
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unsigned long parent_rate;
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unsigned int i;
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long emc_rate;
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int div;
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emc_rate = emc->round_cb(req->rate, req->min_rate, req->max_rate,
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emc->cb_arg);
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if (emc_rate < 0)
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return emc_rate;
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for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
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parent_hw = clk_hw_get_parent_by_index(hw, i);
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if (req->best_parent_hw == parent_hw)
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parent_rate = req->best_parent_rate;
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else
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parent_rate = clk_hw_get_rate(parent_hw);
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if (emc_rate > parent_rate)
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continue;
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div = div_frac_get(emc_rate, parent_rate, 8, 1, 0);
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divided_rate = DIV_ROUND_UP(parent_rate * 2, div + 2);
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if (divided_rate != emc_rate)
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continue;
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req->best_parent_rate = parent_rate;
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req->best_parent_hw = parent_hw;
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req->rate = emc_rate;
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break;
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}
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if (i == ARRAY_SIZE(emc_parent_clk_names)) {
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pr_err_once("can't find parent for rate %lu emc_rate %lu\n",
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req->rate, emc_rate);
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return -EINVAL;
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}
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return 0;
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}
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static const struct clk_ops tegra_clk_emc_ops = {
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.recalc_rate = emc_recalc_rate,
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.get_parent = emc_get_parent,
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.set_parent = emc_set_parent,
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.set_rate = emc_set_rate,
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.set_rate_and_parent = emc_set_rate_and_parent,
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.determine_rate = emc_determine_rate,
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};
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void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
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void *cb_arg)
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{
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struct clk *clk = __clk_lookup("emc");
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struct tegra_clk_emc *emc;
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struct clk_hw *hw;
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if (clk) {
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hw = __clk_get_hw(clk);
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emc = to_tegra_clk_emc(hw);
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emc->round_cb = round_cb;
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emc->cb_arg = cb_arg;
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}
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}
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bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw)
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{
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return to_tegra_clk_emc(emc_hw)->round_cb != NULL;
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}
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struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter)
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{
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struct tegra_clk_emc *emc;
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struct clk_init_data init;
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struct clk *clk;
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emc = kzalloc(sizeof(*emc), GFP_KERNEL);
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if (!emc)
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return NULL;
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/*
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* EMC stands for External Memory Controller.
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*
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* We don't want EMC clock to be disabled ever by gating its
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* parent and whatnot because system is busted immediately in that
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* case, hence the clock is marked as critical.
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*/
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init.name = "emc";
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init.ops = &tegra_clk_emc_ops;
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init.flags = CLK_IS_CRITICAL;
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init.parent_names = emc_parent_clk_names;
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init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
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emc->reg = ioaddr;
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emc->hw.init = &init;
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emc->want_low_jitter = low_jitter;
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clk = clk_register(NULL, &emc->hw);
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if (IS_ERR(clk)) {
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kfree(emc);
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return NULL;
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}
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return clk;
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}
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int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
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{
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struct tegra_clk_emc *emc;
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struct clk_hw *hw;
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if (!emc_clk)
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return -EINVAL;
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hw = __clk_get_hw(emc_clk);
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emc = to_tegra_clk_emc(hw);
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emc->mc_same_freq = same;
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return 0;
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}
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