![Sowjanya Komatineni](/assets/img/avatar_default.png)
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2, clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct PMC register access during clk_ops and these PMC register read and write access will not happen when PMC is in secure mode. Any direct PMC register access from non-secure world will not go through. All the PMC clocks are moved to Tegra PMC driver with PMC as a clock provider. This patch removes tegra_pmc_clk_init along with corresponding clk ids from Tegra clock driver. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
911 lines
29 KiB
C
911 lines
29 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __TEGRA_CLK_H
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#define __TEGRA_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/delay.h>
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#define CLK_OUT_ENB_L 0x010
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#define CLK_OUT_ENB_H 0x014
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#define CLK_OUT_ENB_U 0x018
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#define CLK_OUT_ENB_V 0x360
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#define CLK_OUT_ENB_W 0x364
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#define CLK_OUT_ENB_X 0x280
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#define CLK_OUT_ENB_Y 0x298
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#define CLK_ENB_PLLP_OUT_CPU BIT(31)
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#define CLK_OUT_ENB_SET_L 0x320
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#define CLK_OUT_ENB_CLR_L 0x324
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#define CLK_OUT_ENB_SET_H 0x328
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#define CLK_OUT_ENB_CLR_H 0x32c
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#define CLK_OUT_ENB_SET_U 0x330
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#define CLK_OUT_ENB_CLR_U 0x334
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#define CLK_OUT_ENB_SET_V 0x440
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#define CLK_OUT_ENB_CLR_V 0x444
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#define CLK_OUT_ENB_SET_W 0x448
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#define CLK_OUT_ENB_CLR_W 0x44c
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#define CLK_OUT_ENB_SET_X 0x284
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#define CLK_OUT_ENB_CLR_X 0x288
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#define CLK_OUT_ENB_SET_Y 0x29c
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#define CLK_OUT_ENB_CLR_Y 0x2a0
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#define RST_DEVICES_L 0x004
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#define RST_DEVICES_H 0x008
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#define RST_DEVICES_U 0x00C
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#define RST_DEVICES_V 0x358
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#define RST_DEVICES_W 0x35C
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#define RST_DEVICES_X 0x28C
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#define RST_DEVICES_Y 0x2a4
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#define RST_DEVICES_SET_L 0x300
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#define RST_DEVICES_CLR_L 0x304
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#define RST_DEVICES_SET_H 0x308
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#define RST_DEVICES_CLR_H 0x30c
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#define RST_DEVICES_SET_U 0x310
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#define RST_DEVICES_CLR_U 0x314
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#define RST_DEVICES_SET_V 0x430
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#define RST_DEVICES_CLR_V 0x434
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#define RST_DEVICES_SET_W 0x438
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#define RST_DEVICES_CLR_W 0x43c
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#define RST_DEVICES_SET_X 0x290
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#define RST_DEVICES_CLR_X 0x294
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#define RST_DEVICES_SET_Y 0x2a8
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#define RST_DEVICES_CLR_Y 0x2ac
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/*
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* Tegra CLK_OUT_ENB registers have some undefined bits which are not used and
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* any accidental write of 1 to these bits can cause PSLVERR.
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* So below are the valid mask defines for each CLK_OUT_ENB register used to
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* turn ON only the valid clocks.
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*/
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#define TEGRA210_CLK_ENB_VLD_MSK_L 0xdcd7dff9
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#define TEGRA210_CLK_ENB_VLD_MSK_H 0x87d1f3e7
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#define TEGRA210_CLK_ENB_VLD_MSK_U 0xf3fed3fa
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#define TEGRA210_CLK_ENB_VLD_MSK_V 0xffc18cfb
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#define TEGRA210_CLK_ENB_VLD_MSK_W 0x793fb7ff
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#define TEGRA210_CLK_ENB_VLD_MSK_X 0x3fe66fff
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#define TEGRA210_CLK_ENB_VLD_MSK_Y 0xfc1fc7ff
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/**
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* struct tegra_clk_sync_source - external clock source from codec
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*
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* @hw: handle between common and hardware-specific interfaces
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* @rate: input frequency from source
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* @max_rate: max rate allowed
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*/
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struct tegra_clk_sync_source {
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struct clk_hw hw;
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unsigned long rate;
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unsigned long max_rate;
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};
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#define to_clk_sync_source(_hw) \
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container_of(_hw, struct tegra_clk_sync_source, hw)
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extern const struct clk_ops tegra_clk_sync_source_ops;
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extern int *periph_clk_enb_refcnt;
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struct clk *tegra_clk_register_sync_source(const char *name,
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unsigned long max_rate);
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/**
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* struct tegra_clk_frac_div - fractional divider clock
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*
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* @hw: handle between common and hardware-specific interfaces
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* @reg: register containing divider
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* @flags: hardware-specific flags
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* @shift: shift to the divider bit field
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* @width: width of the divider bit field
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* @frac_width: width of the fractional bit field
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* @lock: register lock
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*
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* Flags:
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* TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
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* TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
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* flag indicates that this divider is for fixed rate PLL.
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* TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
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* fraction bit is set. This flags indicates to calculate divider for which
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* fracton bit will be zero.
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* TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
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* set when divider value is not 0. This flags indicates that the divider
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* is for UART module.
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*/
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struct tegra_clk_frac_div {
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struct clk_hw hw;
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void __iomem *reg;
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u8 flags;
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u8 shift;
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u8 width;
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u8 frac_width;
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spinlock_t *lock;
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};
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#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
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#define TEGRA_DIVIDER_ROUND_UP BIT(0)
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#define TEGRA_DIVIDER_FIXED BIT(1)
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#define TEGRA_DIVIDER_INT BIT(2)
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#define TEGRA_DIVIDER_UART BIT(3)
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extern const struct clk_ops tegra_clk_frac_div_ops;
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struct clk *tegra_clk_register_divider(const char *name,
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const char *parent_name, void __iomem *reg,
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unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
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u8 frac_width, spinlock_t *lock);
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struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
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void __iomem *reg, spinlock_t *lock);
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/*
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* Tegra PLL:
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*
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* In general, there are 3 requirements for each PLL
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* that SW needs to be comply with.
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* (1) Input frequency range (REF).
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* (2) Comparison frequency range (CF). CF = REF/DIVM.
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* (3) VCO frequency range (VCO). VCO = CF * DIVN.
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*
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* The final PLL output frequency (FO) = VCO >> DIVP.
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*/
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/**
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* struct tegra_clk_pll_freq_table - PLL frequecy table
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*
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* @input_rate: input rate from source
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* @output_rate: output rate from PLL for the input rate
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* @n: feedback divider
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* @m: input divider
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* @p: post divider
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* @cpcon: charge pump current
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* @sdm_data: fraction divider setting (0 = disabled)
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*/
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struct tegra_clk_pll_freq_table {
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unsigned long input_rate;
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unsigned long output_rate;
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u32 n;
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u32 m;
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u8 p;
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u8 cpcon;
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u16 sdm_data;
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};
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/**
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* struct pdiv_map - map post divider to hw value
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*
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* @pdiv: post divider
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* @hw_val: value to be written to the PLL hw
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*/
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struct pdiv_map {
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u8 pdiv;
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u8 hw_val;
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};
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/**
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* struct div_nmp - offset and width of m,n and p fields
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*
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* @divn_shift: shift to the feedback divider bit field
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* @divn_width: width of the feedback divider bit field
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* @divm_shift: shift to the input divider bit field
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* @divm_width: width of the input divider bit field
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* @divp_shift: shift to the post divider bit field
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* @divp_width: width of the post divider bit field
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* @override_divn_shift: shift to the feedback divider bitfield in override reg
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* @override_divm_shift: shift to the input divider bitfield in override reg
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* @override_divp_shift: shift to the post divider bitfield in override reg
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*/
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struct div_nmp {
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u8 divn_shift;
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u8 divn_width;
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u8 divm_shift;
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u8 divm_width;
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u8 divp_shift;
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u8 divp_width;
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u8 override_divn_shift;
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u8 override_divm_shift;
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u8 override_divp_shift;
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};
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#define MAX_PLL_MISC_REG_COUNT 6
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struct tegra_clk_pll;
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/**
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* struct tegra_clk_pll_params - PLL parameters
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*
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* @input_min: Minimum input frequency
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* @input_max: Maximum input frequency
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* @cf_min: Minimum comparison frequency
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* @cf_max: Maximum comparison frequency
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* @vco_min: Minimum VCO frequency
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* @vco_max: Maximum VCO frequency
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* @base_reg: PLL base reg offset
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* @misc_reg: PLL misc reg offset
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* @lock_reg: PLL lock reg offset
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* @lock_mask: Bitmask for PLL lock status
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* @lock_enable_bit_idx: Bit index to enable PLL lock
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* @iddq_reg: PLL IDDQ register offset
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* @iddq_bit_idx: Bit index to enable PLL IDDQ
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* @reset_reg: Register offset of where RESET bit is
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* @reset_bit_idx: Shift of reset bit in reset_reg
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* @sdm_din_reg: Register offset where SDM settings are
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* @sdm_din_mask: Mask of SDM divider bits
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* @sdm_ctrl_reg: Register offset where SDM enable is
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* @sdm_ctrl_en_mask: Mask of SDM enable bit
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* @ssc_ctrl_reg: Register offset where SSC settings are
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* @ssc_ctrl_en_mask: Mask of SSC enable bit
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* @aux_reg: AUX register offset
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* @dyn_ramp_reg: Dynamic ramp control register offset
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* @ext_misc_reg: Miscellaneous control register offsets
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* @pmc_divnm_reg: n, m divider PMC override register offset (PLLM)
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* @pmc_divp_reg: p divider PMC override register offset (PLLM)
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* @flags: PLL flags
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* @stepa_shift: Dynamic ramp step A field shift
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* @stepb_shift: Dynamic ramp step B field shift
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* @lock_delay: Delay in us if PLL lock is not used
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* @max_p: maximum value for the p divider
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* @defaults_set: Boolean signaling all reg defaults for PLL set.
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* @pdiv_tohw: mapping of p divider to register values
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* @div_nmp: offsets and widths on n, m and p fields
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* @freq_table: array of frequencies supported by PLL
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* @fixed_rate: PLL rate if it is fixed
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* @mdiv_default: Default value for fixed mdiv for this PLL
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* @round_p_to_pdiv: Callback used to round p to the closed pdiv
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* @set_gain: Callback to adjust N div for SDM enabled
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* PLL's based on fractional divider value.
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* @calc_rate: Callback used to change how out of table
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* rates (dividers and multipler) are calculated.
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* @adjust_vco: Callback to adjust the programming range of the
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* divider range (if SDM is present)
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* @set_defaults: Callback which will try to initialize PLL
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* registers to sane default values. This is first
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* tried during PLL registration, but if the PLL
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* is already enabled, it will be done the first
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* time the rate is changed while the PLL is
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* disabled.
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* @dyn_ramp: Callback which can be used to define a custom
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* dynamic ramp function for a given PLL.
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*
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* Flags:
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* TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
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* PLL locking. If not set it will use lock_delay value to wait.
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* TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
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* to be programmed to change output frequency of the PLL.
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* TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
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* that it is PLLU and invert post divider value.
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* TEGRA_PLLM - PLLM has additional override settings in PMC. This
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* flag indicates that it is PLLM and use override settings.
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* TEGRA_PLL_FIXED - We are not supposed to change output frequency
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* of some plls.
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* TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
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* TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
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* base register.
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* TEGRA_PLL_BYPASS - PLL has bypass bit
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* TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
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* TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
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* it may be more accurate (especially if SDM present)
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* TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
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* flag indicated that it is PLLMB.
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* TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
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*/
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struct tegra_clk_pll_params {
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unsigned long input_min;
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unsigned long input_max;
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unsigned long cf_min;
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unsigned long cf_max;
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unsigned long vco_min;
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unsigned long vco_max;
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u32 base_reg;
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u32 misc_reg;
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u32 lock_reg;
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u32 lock_mask;
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u32 lock_enable_bit_idx;
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u32 iddq_reg;
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u32 iddq_bit_idx;
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u32 reset_reg;
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u32 reset_bit_idx;
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u32 sdm_din_reg;
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u32 sdm_din_mask;
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u32 sdm_ctrl_reg;
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u32 sdm_ctrl_en_mask;
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u32 ssc_ctrl_reg;
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u32 ssc_ctrl_en_mask;
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u32 aux_reg;
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u32 dyn_ramp_reg;
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u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
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u32 pmc_divnm_reg;
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u32 pmc_divp_reg;
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u32 flags;
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int stepa_shift;
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int stepb_shift;
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int lock_delay;
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int max_p;
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bool defaults_set;
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const struct pdiv_map *pdiv_tohw;
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struct div_nmp *div_nmp;
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struct tegra_clk_pll_freq_table *freq_table;
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unsigned long fixed_rate;
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u16 mdiv_default;
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u32 (*round_p_to_pdiv)(u32 p, u32 *pdiv);
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void (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
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int (*calc_rate)(struct clk_hw *hw,
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struct tegra_clk_pll_freq_table *cfg,
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unsigned long rate, unsigned long parent_rate);
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unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
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unsigned long parent_rate);
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void (*set_defaults)(struct tegra_clk_pll *pll);
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int (*dyn_ramp)(struct tegra_clk_pll *pll,
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struct tegra_clk_pll_freq_table *cfg);
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};
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#define TEGRA_PLL_USE_LOCK BIT(0)
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#define TEGRA_PLL_HAS_CPCON BIT(1)
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#define TEGRA_PLL_SET_LFCON BIT(2)
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#define TEGRA_PLL_SET_DCCON BIT(3)
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#define TEGRA_PLLU BIT(4)
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#define TEGRA_PLLM BIT(5)
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#define TEGRA_PLL_FIXED BIT(6)
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#define TEGRA_PLLE_CONFIGURE BIT(7)
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#define TEGRA_PLL_LOCK_MISC BIT(8)
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#define TEGRA_PLL_BYPASS BIT(9)
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#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
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#define TEGRA_MDIV_NEW BIT(11)
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#define TEGRA_PLLMB BIT(12)
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#define TEGRA_PLL_VCO_OUT BIT(13)
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/**
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* struct tegra_clk_pll - Tegra PLL clock
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*
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* @hw: handle between common and hardware-specifix interfaces
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* @clk_base: address of CAR controller
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* @pmc: address of PMC, required to read override bits
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* @lock: register lock
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* @params: PLL parameters
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*/
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struct tegra_clk_pll {
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struct clk_hw hw;
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void __iomem *clk_base;
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void __iomem *pmc;
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spinlock_t *lock;
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struct tegra_clk_pll_params *params;
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};
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#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
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/**
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* struct tegra_audio_clk_info - Tegra Audio Clk Information
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*
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* @name: name for the audio pll
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* @pll_params: pll_params for audio pll
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* @clk_id: clk_ids for the audio pll
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* @parent: name of the parent of the audio pll
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*/
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struct tegra_audio_clk_info {
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char *name;
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struct tegra_clk_pll_params *pll_params;
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int clk_id;
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char *parent;
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};
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extern const struct clk_ops tegra_clk_pll_ops;
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extern const struct clk_ops tegra_clk_plle_ops;
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struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags, struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags, struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
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struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
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void __iomem *clk_base, void __iomem *pmc,
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unsigned long flags,
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struct tegra_clk_pll_params *pll_params,
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spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
|
|
void __iomem *clk_base, void __iomem *pmc,
|
|
unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock, unsigned long parent_rate);
|
|
|
|
struct clk *tegra_clk_register_pllre_tegra210(const char *name,
|
|
const char *parent_name, void __iomem *clk_base,
|
|
void __iomem *pmc, unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock, unsigned long parent_rate);
|
|
|
|
struct clk *tegra_clk_register_plle_tegra114(const char *name,
|
|
const char *parent_name,
|
|
void __iomem *clk_base, unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_plle_tegra210(const char *name,
|
|
const char *parent_name,
|
|
void __iomem *clk_base, unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_pllc_tegra210(const char *name,
|
|
const char *parent_name, void __iomem *clk_base,
|
|
void __iomem *pmc, unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_pllss_tegra210(const char *name,
|
|
const char *parent_name, void __iomem *clk_base,
|
|
unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
|
|
void __iomem *clk_base, unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
|
|
void __iomem *clk_base, void __iomem *pmc,
|
|
unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
|
|
void __iomem *clk_base, unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_pllu_tegra114(const char *name,
|
|
const char *parent_name,
|
|
void __iomem *clk_base, unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
struct clk *tegra_clk_register_pllu_tegra210(const char *name,
|
|
const char *parent_name,
|
|
void __iomem *clk_base, unsigned long flags,
|
|
struct tegra_clk_pll_params *pll_params,
|
|
spinlock_t *lock);
|
|
|
|
/**
|
|
* struct tegra_clk_pll_out - PLL divider down clock
|
|
*
|
|
* @hw: handle between common and hardware-specific interfaces
|
|
* @reg: register containing the PLL divider
|
|
* @enb_bit_idx: bit to enable/disable PLL divider
|
|
* @rst_bit_idx: bit to reset PLL divider
|
|
* @lock: register lock
|
|
* @flags: hardware-specific flags
|
|
*/
|
|
struct tegra_clk_pll_out {
|
|
struct clk_hw hw;
|
|
void __iomem *reg;
|
|
u8 enb_bit_idx;
|
|
u8 rst_bit_idx;
|
|
spinlock_t *lock;
|
|
u8 flags;
|
|
};
|
|
|
|
#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
|
|
|
|
extern const struct clk_ops tegra_clk_pll_out_ops;
|
|
struct clk *tegra_clk_register_pll_out(const char *name,
|
|
const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
|
|
u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
|
|
spinlock_t *lock);
|
|
|
|
/**
|
|
* struct tegra_clk_periph_regs - Registers controlling peripheral clock
|
|
*
|
|
* @enb_reg: read the enable status
|
|
* @enb_set_reg: write 1 to enable clock
|
|
* @enb_clr_reg: write 1 to disable clock
|
|
* @rst_reg: read the reset status
|
|
* @rst_set_reg: write 1 to assert the reset of peripheral
|
|
* @rst_clr_reg: write 1 to deassert the reset of peripheral
|
|
*/
|
|
struct tegra_clk_periph_regs {
|
|
u32 enb_reg;
|
|
u32 enb_set_reg;
|
|
u32 enb_clr_reg;
|
|
u32 rst_reg;
|
|
u32 rst_set_reg;
|
|
u32 rst_clr_reg;
|
|
};
|
|
|
|
/**
|
|
* struct tegra_clk_periph_gate - peripheral gate clock
|
|
*
|
|
* @magic: magic number to validate type
|
|
* @hw: handle between common and hardware-specific interfaces
|
|
* @clk_base: address of CAR controller
|
|
* @regs: Registers to control the peripheral
|
|
* @flags: hardware-specific flags
|
|
* @clk_num: Clock number
|
|
* @enable_refcnt: array to maintain reference count of the clock
|
|
*
|
|
* Flags:
|
|
* TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
|
|
* for this module.
|
|
* TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
|
|
* after clock enable and driver for the module is responsible for
|
|
* doing reset.
|
|
* TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
|
|
* bus to flush the write operation in apb bus. This flag indicates
|
|
* that this peripheral is in apb bus.
|
|
* TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
|
|
*/
|
|
struct tegra_clk_periph_gate {
|
|
u32 magic;
|
|
struct clk_hw hw;
|
|
void __iomem *clk_base;
|
|
u8 flags;
|
|
int clk_num;
|
|
int *enable_refcnt;
|
|
const struct tegra_clk_periph_regs *regs;
|
|
};
|
|
|
|
#define to_clk_periph_gate(_hw) \
|
|
container_of(_hw, struct tegra_clk_periph_gate, hw)
|
|
|
|
#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
|
|
|
|
#define TEGRA_PERIPH_NO_RESET BIT(0)
|
|
#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
|
|
#define TEGRA_PERIPH_ON_APB BIT(2)
|
|
#define TEGRA_PERIPH_WAR_1005168 BIT(3)
|
|
#define TEGRA_PERIPH_NO_DIV BIT(4)
|
|
#define TEGRA_PERIPH_NO_GATE BIT(5)
|
|
|
|
extern const struct clk_ops tegra_clk_periph_gate_ops;
|
|
struct clk *tegra_clk_register_periph_gate(const char *name,
|
|
const char *parent_name, u8 gate_flags, void __iomem *clk_base,
|
|
unsigned long flags, int clk_num, int *enable_refcnt);
|
|
|
|
struct tegra_clk_periph_fixed {
|
|
struct clk_hw hw;
|
|
void __iomem *base;
|
|
const struct tegra_clk_periph_regs *regs;
|
|
unsigned int mul;
|
|
unsigned int div;
|
|
unsigned int num;
|
|
};
|
|
|
|
struct clk *tegra_clk_register_periph_fixed(const char *name,
|
|
const char *parent,
|
|
unsigned long flags,
|
|
void __iomem *base,
|
|
unsigned int mul,
|
|
unsigned int div,
|
|
unsigned int num);
|
|
|
|
/**
|
|
* struct clk-periph - peripheral clock
|
|
*
|
|
* @magic: magic number to validate type
|
|
* @hw: handle between common and hardware-specific interfaces
|
|
* @mux: mux clock
|
|
* @divider: divider clock
|
|
* @gate: gate clock
|
|
* @mux_ops: mux clock ops
|
|
* @div_ops: divider clock ops
|
|
* @gate_ops: gate clock ops
|
|
*/
|
|
struct tegra_clk_periph {
|
|
u32 magic;
|
|
struct clk_hw hw;
|
|
struct clk_mux mux;
|
|
struct tegra_clk_frac_div divider;
|
|
struct tegra_clk_periph_gate gate;
|
|
|
|
const struct clk_ops *mux_ops;
|
|
const struct clk_ops *div_ops;
|
|
const struct clk_ops *gate_ops;
|
|
};
|
|
|
|
#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
|
|
|
|
#define TEGRA_CLK_PERIPH_MAGIC 0x18221223
|
|
|
|
extern const struct clk_ops tegra_clk_periph_ops;
|
|
struct clk *tegra_clk_register_periph(const char *name,
|
|
const char * const *parent_names, int num_parents,
|
|
struct tegra_clk_periph *periph, void __iomem *clk_base,
|
|
u32 offset, unsigned long flags);
|
|
struct clk *tegra_clk_register_periph_nodiv(const char *name,
|
|
const char * const *parent_names, int num_parents,
|
|
struct tegra_clk_periph *periph, void __iomem *clk_base,
|
|
u32 offset);
|
|
|
|
#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
|
|
_div_shift, _div_width, _div_frac_width, \
|
|
_div_flags, _clk_num,\
|
|
_gate_flags, _table, _lock) \
|
|
{ \
|
|
.mux = { \
|
|
.flags = _mux_flags, \
|
|
.shift = _mux_shift, \
|
|
.mask = _mux_mask, \
|
|
.table = _table, \
|
|
.lock = _lock, \
|
|
}, \
|
|
.divider = { \
|
|
.flags = _div_flags, \
|
|
.shift = _div_shift, \
|
|
.width = _div_width, \
|
|
.frac_width = _div_frac_width, \
|
|
.lock = _lock, \
|
|
}, \
|
|
.gate = { \
|
|
.flags = _gate_flags, \
|
|
.clk_num = _clk_num, \
|
|
}, \
|
|
.mux_ops = &clk_mux_ops, \
|
|
.div_ops = &tegra_clk_frac_div_ops, \
|
|
.gate_ops = &tegra_clk_periph_gate_ops, \
|
|
}
|
|
|
|
struct tegra_periph_init_data {
|
|
const char *name;
|
|
int clk_id;
|
|
union {
|
|
const char *const *parent_names;
|
|
const char *parent_name;
|
|
} p;
|
|
int num_parents;
|
|
struct tegra_clk_periph periph;
|
|
u32 offset;
|
|
const char *con_id;
|
|
const char *dev_id;
|
|
unsigned long flags;
|
|
};
|
|
|
|
#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
|
|
_mux_shift, _mux_mask, _mux_flags, _div_shift, \
|
|
_div_width, _div_frac_width, _div_flags, \
|
|
_clk_num, _gate_flags, _clk_id, _table, \
|
|
_flags, _lock) \
|
|
{ \
|
|
.name = _name, \
|
|
.clk_id = _clk_id, \
|
|
.p.parent_names = _parent_names, \
|
|
.num_parents = ARRAY_SIZE(_parent_names), \
|
|
.periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
|
|
_mux_flags, _div_shift, \
|
|
_div_width, _div_frac_width, \
|
|
_div_flags, _clk_num, \
|
|
_gate_flags, _table, _lock), \
|
|
.offset = _offset, \
|
|
.con_id = _con_id, \
|
|
.dev_id = _dev_id, \
|
|
.flags = _flags \
|
|
}
|
|
|
|
#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
|
|
_mux_shift, _mux_width, _mux_flags, _div_shift, \
|
|
_div_width, _div_frac_width, _div_flags, \
|
|
_clk_num, _gate_flags, _clk_id) \
|
|
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
|
|
_mux_shift, BIT(_mux_width) - 1, _mux_flags, \
|
|
_div_shift, _div_width, _div_frac_width, _div_flags, \
|
|
_clk_num, _gate_flags, _clk_id,\
|
|
NULL, 0, NULL)
|
|
|
|
struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
|
|
struct tegra_periph_init_data *init);
|
|
|
|
/**
|
|
* struct clk_super_mux - super clock
|
|
*
|
|
* @hw: handle between common and hardware-specific interfaces
|
|
* @reg: register controlling multiplexer
|
|
* @width: width of the multiplexer bit field
|
|
* @flags: hardware-specific flags
|
|
* @div2_index: bit controlling divide-by-2
|
|
* @pllx_index: PLLX index in the parent list
|
|
* @lock: register lock
|
|
*
|
|
* Flags:
|
|
* TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
|
|
* that this is LP cluster clock.
|
|
* TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
|
|
* super mux parent using PLLP branches. To use PLLP branches to CPU, need
|
|
* to configure additional bit PLLP_OUT_CPU in the clock registers.
|
|
*/
|
|
struct tegra_clk_super_mux {
|
|
struct clk_hw hw;
|
|
void __iomem *reg;
|
|
struct tegra_clk_frac_div frac_div;
|
|
const struct clk_ops *div_ops;
|
|
u8 width;
|
|
u8 flags;
|
|
u8 div2_index;
|
|
u8 pllx_index;
|
|
spinlock_t *lock;
|
|
};
|
|
|
|
#define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
|
|
|
|
#define TEGRA_DIVIDER_2 BIT(0)
|
|
#define TEGRA210_CPU_CLK BIT(1)
|
|
|
|
extern const struct clk_ops tegra_clk_super_ops;
|
|
struct clk *tegra_clk_register_super_mux(const char *name,
|
|
const char **parent_names, u8 num_parents,
|
|
unsigned long flags, void __iomem *reg, u8 clk_super_flags,
|
|
u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
|
|
struct clk *tegra_clk_register_super_clk(const char *name,
|
|
const char * const *parent_names, u8 num_parents,
|
|
unsigned long flags, void __iomem *reg, u8 clk_super_flags,
|
|
spinlock_t *lock);
|
|
|
|
/**
|
|
* struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
|
|
*
|
|
* @hw: handle between common and hardware-specific interfaces
|
|
* @reg: register controlling mux and divider
|
|
* @flags: hardware-specific flags
|
|
* @lock: optional register lock
|
|
* @gate: gate clock
|
|
* @gate_ops: gate clock ops
|
|
*/
|
|
struct tegra_sdmmc_mux {
|
|
struct clk_hw hw;
|
|
void __iomem *reg;
|
|
spinlock_t *lock;
|
|
const struct clk_ops *gate_ops;
|
|
struct tegra_clk_periph_gate gate;
|
|
u8 div_flags;
|
|
};
|
|
|
|
#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw)
|
|
|
|
struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
|
|
void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
|
|
unsigned long flags, void *lock);
|
|
|
|
/**
|
|
* struct clk_init_table - clock initialization table
|
|
* @clk_id: clock id as mentioned in device tree bindings
|
|
* @parent_id: parent clock id as mentioned in device tree bindings
|
|
* @rate: rate to set
|
|
* @state: enable/disable
|
|
*/
|
|
struct tegra_clk_init_table {
|
|
unsigned int clk_id;
|
|
unsigned int parent_id;
|
|
unsigned long rate;
|
|
int state;
|
|
};
|
|
|
|
/**
|
|
* struct clk_duplicate - duplicate clocks
|
|
* @clk_id: clock id as mentioned in device tree bindings
|
|
* @lookup: duplicate lookup entry for the clock
|
|
*/
|
|
struct tegra_clk_duplicate {
|
|
int clk_id;
|
|
struct clk_lookup lookup;
|
|
};
|
|
|
|
#define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
|
|
{ \
|
|
.clk_id = _clk_id, \
|
|
.lookup = { \
|
|
.dev_id = _dev, \
|
|
.con_id = _con, \
|
|
}, \
|
|
}
|
|
|
|
struct tegra_clk {
|
|
int dt_id;
|
|
bool present;
|
|
};
|
|
|
|
struct tegra_devclk {
|
|
int dt_id;
|
|
char *dev_id;
|
|
char *con_id;
|
|
};
|
|
|
|
void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long),
|
|
int (*deassert)(unsigned long));
|
|
|
|
void tegra_init_from_table(struct tegra_clk_init_table *tbl,
|
|
struct clk *clks[], int clk_max);
|
|
|
|
void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
|
|
struct clk *clks[], int clk_max);
|
|
|
|
const struct tegra_clk_periph_regs *get_reg_bank(int clkid);
|
|
struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
|
|
|
|
struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
|
|
|
|
void tegra_add_of_provider(struct device_node *np, void *clk_src_onecell_get);
|
|
void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
|
|
|
|
void tegra_audio_clk_init(void __iomem *clk_base,
|
|
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
|
struct tegra_audio_clk_info *audio_info,
|
|
unsigned int num_plls, unsigned long sync_max_rate);
|
|
|
|
void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
|
|
struct tegra_clk *tegra_clks,
|
|
struct tegra_clk_pll_params *pll_params);
|
|
|
|
void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
|
|
int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
|
|
unsigned long *input_freqs, unsigned int num,
|
|
unsigned int clk_m_div, unsigned long *osc_freq,
|
|
unsigned long *pll_ref_freq);
|
|
void tegra_super_clk_gen4_init(void __iomem *clk_base,
|
|
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
|
struct tegra_clk_pll_params *pll_params);
|
|
void tegra_super_clk_gen5_init(void __iomem *clk_base,
|
|
void __iomem *pmc_base, struct tegra_clk *tegra_clks,
|
|
struct tegra_clk_pll_params *pll_params);
|
|
|
|
#ifdef CONFIG_TEGRA_CLK_EMC
|
|
struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
|
|
spinlock_t *lock);
|
|
#else
|
|
static inline struct clk *tegra_clk_register_emc(void __iomem *base,
|
|
struct device_node *np,
|
|
spinlock_t *lock)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
void tegra114_clock_tune_cpu_trimmers_high(void);
|
|
void tegra114_clock_tune_cpu_trimmers_low(void);
|
|
void tegra114_clock_tune_cpu_trimmers_init(void);
|
|
void tegra114_clock_assert_dfll_dvco_reset(void);
|
|
void tegra114_clock_deassert_dfll_dvco_reset(void);
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typedef void (*tegra_clk_apply_init_table_func)(void);
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extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
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int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
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u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
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int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
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int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
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u8 frac_width, u8 flags);
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void tegra_clk_osc_resume(void __iomem *clk_base);
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void tegra_clk_set_pllp_out_cpu(bool enable);
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void tegra_clk_periph_suspend(void);
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void tegra_clk_periph_resume(void);
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/* Combined read fence with delay */
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#define fence_udelay(delay, reg) \
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do { \
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readl(reg); \
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udelay(delay); \
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} while (0)
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bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw);
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struct clk *tegra20_clk_register_emc(void __iomem *ioaddr, bool low_jitter);
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#endif /* TEGRA_CLK_H */
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