![Laurent Pinchart](/assets/img/avatar_default.png)
The "Renesas Corporation" listed in the copyright notice doesn't exist. Replace it with "Renesas Electronics Corporation" and update the copyright years. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
611 lines
16 KiB
C
611 lines
16 KiB
C
/*
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* rcar_du_crtc.c -- R-Car Display Unit CRTCs
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include "rcar_du_crtc.h"
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#include "rcar_du_drv.h"
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#include "rcar_du_kms.h"
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#include "rcar_du_plane.h"
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#include "rcar_du_regs.h"
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static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
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}
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static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
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}
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static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
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rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
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}
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static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
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rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
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}
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static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
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u32 clr, u32 set)
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{
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
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rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
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}
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static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
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{
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int ret;
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ret = clk_prepare_enable(rcrtc->clock);
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if (ret < 0)
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return ret;
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ret = rcar_du_group_get(rcrtc->group);
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if (ret < 0)
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clk_disable_unprepare(rcrtc->clock);
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return ret;
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}
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static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
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{
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rcar_du_group_put(rcrtc->group);
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clk_disable_unprepare(rcrtc->clock);
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}
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static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
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{
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const struct drm_display_mode *mode = &rcrtc->crtc.mode;
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unsigned long clk;
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u32 value;
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u32 div;
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/* Dot clock */
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clk = clk_get_rate(rcrtc->clock);
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div = DIV_ROUND_CLOSEST(clk, mode->clock * 1000);
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div = clamp(div, 1U, 64U) - 1;
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
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ESCR_DCLKSEL_CLKS | div);
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
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/* Signal polarities */
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value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
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| ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
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| DSMR_DIPM_DE;
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rcar_du_crtc_write(rcrtc, DSMR, value);
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/* Display timings */
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rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
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rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
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mode->hdisplay - 19);
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rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
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mode->hsync_start - 1);
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rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
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rcar_du_crtc_write(rcrtc, VDSR, mode->vtotal - mode->vsync_end - 2);
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rcar_du_crtc_write(rcrtc, VDER, mode->vtotal - mode->vsync_end +
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mode->vdisplay - 2);
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rcar_du_crtc_write(rcrtc, VSPR, mode->vtotal - mode->vsync_end +
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mode->vsync_start - 1);
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rcar_du_crtc_write(rcrtc, VCR, mode->vtotal - 1);
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rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
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rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
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}
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void rcar_du_crtc_route_output(struct drm_crtc *crtc,
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enum rcar_du_output output)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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/* Store the route from the CRTC output to the DU output. The DU will be
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* configured when starting the CRTC.
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*/
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rcrtc->outputs |= BIT(output);
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/* Store RGB routing to DPAD0 for R8A7790. */
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if (rcar_du_has(rcdu, RCAR_DU_FEATURE_DEFR8) &&
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output == RCAR_DU_OUTPUT_DPAD0)
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rcdu->dpad0_source = rcrtc->index;
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}
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void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
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unsigned int num_planes = 0;
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unsigned int prio = 0;
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unsigned int i;
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u32 dptsr = 0;
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u32 dspr = 0;
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for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
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struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
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unsigned int j;
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if (plane->crtc != &rcrtc->crtc || !plane->enabled)
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continue;
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/* Insert the plane in the sorted planes array. */
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for (j = num_planes++; j > 0; --j) {
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if (planes[j-1]->zpos <= plane->zpos)
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break;
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planes[j] = planes[j-1];
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}
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planes[j] = plane;
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prio += plane->format->planes * 4;
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}
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for (i = 0; i < num_planes; ++i) {
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struct rcar_du_plane *plane = planes[i];
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unsigned int index = plane->hwindex;
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prio -= 4;
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dspr |= (index + 1) << prio;
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dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
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if (plane->format->planes == 2) {
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index = (index + 1) % 8;
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prio -= 4;
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dspr |= (index + 1) << prio;
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dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
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}
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}
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/* Select display timing and dot clock generator 2 for planes associated
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* with superposition controller 2.
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*/
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if (rcrtc->index % 2) {
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u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
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/* The DPTSR register is updated when the display controller is
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* stopped. We thus need to restart the DU. Once again, sorry
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* for the flicker. One way to mitigate the issue would be to
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* pre-associate planes with CRTCs (either with a fixed 4/4
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* split, or through a module parameter). Flicker would then
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* occur only if we need to break the pre-association.
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*/
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if (value != dptsr) {
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rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
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if (rcrtc->group->used_crtcs)
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rcar_du_group_restart(rcrtc->group);
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}
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}
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rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
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dspr);
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}
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static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
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{
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struct drm_crtc *crtc = &rcrtc->crtc;
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unsigned int i;
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if (rcrtc->started)
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return;
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if (WARN_ON(rcrtc->plane->format == NULL))
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return;
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/* Set display off and background to black */
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rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
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rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
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/* Configure display timings and output routing */
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rcar_du_crtc_set_display_timing(rcrtc);
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rcar_du_group_set_routing(rcrtc->group);
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mutex_lock(&rcrtc->group->planes.lock);
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rcrtc->plane->enabled = true;
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rcar_du_crtc_update_planes(crtc);
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mutex_unlock(&rcrtc->group->planes.lock);
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/* Setup planes. */
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for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
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struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
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if (plane->crtc != crtc || !plane->enabled)
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continue;
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rcar_du_plane_setup(plane);
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}
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/* Select master sync mode. This enables display operation in master
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* sync mode (with the HSYNC and VSYNC signals configured as outputs and
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* actively driven).
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*/
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rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_MASTER);
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rcar_du_group_start_stop(rcrtc->group, true);
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rcrtc->started = true;
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}
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static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
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{
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struct drm_crtc *crtc = &rcrtc->crtc;
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if (!rcrtc->started)
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return;
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mutex_lock(&rcrtc->group->planes.lock);
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rcrtc->plane->enabled = false;
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rcar_du_crtc_update_planes(crtc);
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mutex_unlock(&rcrtc->group->planes.lock);
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/* Select switch sync mode. This stops display operation and configures
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* the HSYNC and VSYNC signals as inputs.
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*/
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rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
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rcar_du_group_start_stop(rcrtc->group, false);
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rcrtc->started = false;
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}
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void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
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{
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rcar_du_crtc_stop(rcrtc);
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rcar_du_crtc_put(rcrtc);
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}
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void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
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{
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if (rcrtc->dpms != DRM_MODE_DPMS_ON)
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return;
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rcar_du_crtc_get(rcrtc);
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rcar_du_crtc_start(rcrtc);
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}
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static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
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{
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struct drm_crtc *crtc = &rcrtc->crtc;
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rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
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rcar_du_plane_update_base(rcrtc->plane);
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}
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static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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if (rcrtc->dpms == mode)
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return;
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if (mode == DRM_MODE_DPMS_ON) {
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rcar_du_crtc_get(rcrtc);
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rcar_du_crtc_start(rcrtc);
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} else {
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rcar_du_crtc_stop(rcrtc);
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rcar_du_crtc_put(rcrtc);
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}
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rcrtc->dpms = mode;
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}
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static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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/* TODO Fixup modes */
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return true;
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}
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static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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/* We need to access the hardware during mode set, acquire a reference
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* to the CRTC.
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*/
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rcar_du_crtc_get(rcrtc);
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/* Stop the CRTC and release the plane. Force the DPMS mode to off as a
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* result.
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*/
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rcar_du_crtc_stop(rcrtc);
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rcar_du_plane_release(rcrtc->plane);
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rcrtc->dpms = DRM_MODE_DPMS_OFF;
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}
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static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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struct rcar_du_device *rcdu = rcrtc->group->dev;
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const struct rcar_du_format_info *format;
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int ret;
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format = rcar_du_format_info(crtc->primary->fb->pixel_format);
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if (format == NULL) {
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dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
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crtc->primary->fb->pixel_format);
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ret = -EINVAL;
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goto error;
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}
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ret = rcar_du_plane_reserve(rcrtc->plane, format);
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if (ret < 0)
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goto error;
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rcrtc->plane->format = format;
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rcrtc->plane->src_x = x;
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rcrtc->plane->src_y = y;
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rcrtc->plane->width = mode->hdisplay;
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rcrtc->plane->height = mode->vdisplay;
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rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
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rcrtc->outputs = 0;
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return 0;
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error:
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/* There's no rollback/abort operation to clean up in case of error. We
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* thus need to release the reference to the CRTC acquired in prepare()
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* here.
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*/
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rcar_du_crtc_put(rcrtc);
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return ret;
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}
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static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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/* We're done, restart the CRTC and set the DPMS mode to on. The
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* reference to the DU acquired at prepare() time will thus be released
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* by the DPMS handler (possibly called by the disable() handler).
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*/
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rcar_du_crtc_start(rcrtc);
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rcrtc->dpms = DRM_MODE_DPMS_ON;
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}
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static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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rcrtc->plane->src_x = x;
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rcrtc->plane->src_y = y;
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rcar_du_crtc_update_base(rcrtc);
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return 0;
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}
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static void rcar_du_crtc_disable(struct drm_crtc *crtc)
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{
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
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rcar_du_plane_release(rcrtc->plane);
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}
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static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
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.dpms = rcar_du_crtc_dpms,
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.mode_fixup = rcar_du_crtc_mode_fixup,
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.prepare = rcar_du_crtc_mode_prepare,
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.commit = rcar_du_crtc_mode_commit,
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.mode_set = rcar_du_crtc_mode_set,
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.mode_set_base = rcar_du_crtc_mode_set_base,
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.disable = rcar_du_crtc_disable,
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};
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void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
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struct drm_file *file)
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{
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struct drm_pending_vblank_event *event;
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struct drm_device *dev = rcrtc->crtc.dev;
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unsigned long flags;
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/* Destroy the pending vertical blanking event associated with the
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* pending page flip, if any, and disable vertical blanking interrupts.
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*/
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spin_lock_irqsave(&dev->event_lock, flags);
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event = rcrtc->event;
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if (event && event->base.file_priv == file) {
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rcrtc->event = NULL;
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event->base.destroy(&event->base);
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drm_vblank_put(dev, rcrtc->index);
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}
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
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{
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struct drm_pending_vblank_event *event;
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struct drm_device *dev = rcrtc->crtc.dev;
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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event = rcrtc->event;
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rcrtc->event = NULL;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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if (event == NULL)
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return;
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spin_lock_irqsave(&dev->event_lock, flags);
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|
drm_send_vblank_event(dev, rcrtc->index, event);
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
drm_vblank_put(dev, rcrtc->index);
|
|
}
|
|
|
|
static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
|
|
{
|
|
struct rcar_du_crtc *rcrtc = arg;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
u32 status;
|
|
|
|
status = rcar_du_crtc_read(rcrtc, DSSR);
|
|
rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
|
|
|
|
if (status & DSSR_VBK) {
|
|
drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
|
|
rcar_du_crtc_finish_page_flip(rcrtc);
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
struct drm_pending_vblank_event *event,
|
|
uint32_t page_flip_flags)
|
|
{
|
|
struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
|
|
struct drm_device *dev = rcrtc->crtc.dev;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
if (rcrtc->event != NULL) {
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
return -EBUSY;
|
|
}
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
crtc->primary->fb = fb;
|
|
rcar_du_crtc_update_base(rcrtc);
|
|
|
|
if (event) {
|
|
event->pipe = rcrtc->index;
|
|
drm_vblank_get(dev, rcrtc->index);
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
rcrtc->event = event;
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_crtc_funcs crtc_funcs = {
|
|
.destroy = drm_crtc_cleanup,
|
|
.set_config = drm_crtc_helper_set_config,
|
|
.page_flip = rcar_du_crtc_page_flip,
|
|
};
|
|
|
|
int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
|
|
{
|
|
static const unsigned int mmio_offsets[] = {
|
|
DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
|
|
};
|
|
|
|
struct rcar_du_device *rcdu = rgrp->dev;
|
|
struct platform_device *pdev = to_platform_device(rcdu->dev);
|
|
struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
|
|
struct drm_crtc *crtc = &rcrtc->crtc;
|
|
unsigned int irqflags;
|
|
char clk_name[5];
|
|
char *name;
|
|
int irq;
|
|
int ret;
|
|
|
|
/* Get the CRTC clock. */
|
|
if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
|
|
sprintf(clk_name, "du.%u", index);
|
|
name = clk_name;
|
|
} else {
|
|
name = NULL;
|
|
}
|
|
|
|
rcrtc->clock = devm_clk_get(rcdu->dev, name);
|
|
if (IS_ERR(rcrtc->clock)) {
|
|
dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
|
|
return PTR_ERR(rcrtc->clock);
|
|
}
|
|
|
|
rcrtc->group = rgrp;
|
|
rcrtc->mmio_offset = mmio_offsets[index];
|
|
rcrtc->index = index;
|
|
rcrtc->dpms = DRM_MODE_DPMS_OFF;
|
|
rcrtc->plane = &rgrp->planes.planes[index % 2];
|
|
|
|
rcrtc->plane->crtc = crtc;
|
|
|
|
ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
drm_crtc_helper_add(crtc, &crtc_helper_funcs);
|
|
|
|
/* Register the interrupt handler. */
|
|
if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
|
|
irq = platform_get_irq(pdev, index);
|
|
irqflags = 0;
|
|
} else {
|
|
irq = platform_get_irq(pdev, 0);
|
|
irqflags = IRQF_SHARED;
|
|
}
|
|
|
|
if (irq < 0) {
|
|
dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
|
|
dev_name(rcdu->dev), rcrtc);
|
|
if (ret < 0) {
|
|
dev_err(rcdu->dev,
|
|
"failed to register IRQ for CRTC %u\n", index);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
|
|
{
|
|
if (enable) {
|
|
rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
|
|
rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
|
|
} else {
|
|
rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
|
|
}
|
|
}
|