4f246ba30e
The OpenRISC architecture uses the device tree infrastructure for the platform description. This is currently limited to having a device tree built into the kernel, but work is underway within the OpenRISC project to define how this device tree blob should be passed into the kernel from an external resource. Patch contains a single example DTS file to go with the defconfig for or1ksim. Signed-off-by: Jonas Bonn <jonas@southpole.se> Cc: devicetree-discuss@lists.ozlabs.org Reviewed-by: Arnd Bergmann <arnd@arndb.de>
51 lines
982 B
Plaintext
51 lines
982 B
Plaintext
/dts-v1/;
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/ {
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compatible = "opencores,or1ksim";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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chosen {
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bootargs = "console=uart,mmio,0x90000000,115200";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x02000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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clock-frequency = <20000000>;
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};
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};
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/*
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* OR1K PIC is built into CPU and accessed via special purpose
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* registers. It is not addressable and, hence, has no 'reg'
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* property.
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*/
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pic: pic {
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compatible = "opencores,or1k-pic";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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serial0: serial@90000000 {
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compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
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reg = <0x90000000 0x100>;
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interrupts = <2>;
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clock-frequency = <20000000>;
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};
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enet0: ethoc@92000000 {
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compatible = "opencores,ethmac-rtlsvn338";
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reg = <0x92000000 0x100>;
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interrupts = <4>;
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};
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};
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