![Linus Torvalds](/assets/img/avatar_default.png)
Pull irq updates from Thomas Gleixner: "Two patches from the irq departement: - a simple fix to make dummy_irq_chip usable for wakeup scenarios - removal of the gic arch_extn hackery. Now that all users are converted we really want to get rid of the interface so people wont come up with new use cases" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: gic: Drop support for gic_arch_extn genirq: Set IRQCHIP_SKIP_SET_WAKE flag for dummy_irq_chip
1145 lines
29 KiB
C
1145 lines
29 KiB
C
/*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Interrupt architecture for the GIC:
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*
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* o There is one Interrupt Distributor, which receives interrupts
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* from system devices and sends them to the Interrupt Controllers.
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*
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* o There is one CPU Interface per CPU, which sends interrupts sent
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* by the Distributor, and interrupts generated locally, to the
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* associated CPU. The base address of the CPU interface is usually
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* aliased so that the same address points to different chips depending
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* on the CPU it is accessed from.
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*
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* Note that IRQs 0-31 are special - they are local to each CPU.
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* As such, the enable set/clear, pending set/clear and active bit
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* registers are banked per-cpu for these sources.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/cpu_pm.h>
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#include <linux/cpumask.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/acpi.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/arm-gic-acpi.h>
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#include <asm/cputype.h>
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#include <asm/irq.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include "irq-gic-common.h"
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#include "irqchip.h"
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union gic_base {
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void __iomem *common_base;
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void __percpu * __iomem *percpu_base;
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};
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struct gic_chip_data {
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union gic_base dist_base;
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union gic_base cpu_base;
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#ifdef CONFIG_CPU_PM
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u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
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u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
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u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
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u32 __percpu *saved_ppi_enable;
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u32 __percpu *saved_ppi_conf;
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#endif
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struct irq_domain *domain;
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unsigned int gic_irqs;
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#ifdef CONFIG_GIC_NON_BANKED
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void __iomem *(*get_base)(union gic_base *);
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#endif
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};
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static DEFINE_RAW_SPINLOCK(irq_controller_lock);
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/*
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* The GIC mapping of CPU interfaces does not necessarily match
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* the logical CPU numbering. Let's use a mapping as returned
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* by the GIC itself.
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*/
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#define NR_GIC_CPU_IF 8
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static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
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#ifndef MAX_GIC_NR
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#define MAX_GIC_NR 1
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#endif
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static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
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#ifdef CONFIG_GIC_NON_BANKED
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static void __iomem *gic_get_percpu_base(union gic_base *base)
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{
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return raw_cpu_read(*base->percpu_base);
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}
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static void __iomem *gic_get_common_base(union gic_base *base)
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{
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return base->common_base;
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}
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static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
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{
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return data->get_base(&data->dist_base);
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}
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static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
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{
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return data->get_base(&data->cpu_base);
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}
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static inline void gic_set_base_accessor(struct gic_chip_data *data,
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void __iomem *(*f)(union gic_base *))
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{
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data->get_base = f;
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}
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#else
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#define gic_data_dist_base(d) ((d)->dist_base.common_base)
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#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
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#define gic_set_base_accessor(d, f)
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#endif
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static inline void __iomem *gic_dist_base(struct irq_data *d)
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{
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struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
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return gic_data_dist_base(gic_data);
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}
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static inline void __iomem *gic_cpu_base(struct irq_data *d)
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{
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struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
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return gic_data_cpu_base(gic_data);
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}
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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return d->hwirq;
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}
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/*
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* Routines to acknowledge, disable and enable interrupts
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*/
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static void gic_poke_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
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}
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static int gic_peek_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
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}
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static void gic_mask_irq(struct irq_data *d)
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{
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gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
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}
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static void gic_unmask_irq(struct irq_data *d)
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{
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gic_poke_irq(d, GIC_DIST_ENABLE_SET);
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}
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static void gic_eoi_irq(struct irq_data *d)
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{
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writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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}
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static int gic_irq_set_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool val)
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{
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u32 reg;
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switch (which) {
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case IRQCHIP_STATE_PENDING:
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reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
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break;
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case IRQCHIP_STATE_ACTIVE:
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reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
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break;
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case IRQCHIP_STATE_MASKED:
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reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
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break;
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default:
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return -EINVAL;
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}
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gic_poke_irq(d, reg);
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return 0;
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}
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static int gic_irq_get_irqchip_state(struct irq_data *d,
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enum irqchip_irq_state which, bool *val)
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{
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switch (which) {
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case IRQCHIP_STATE_PENDING:
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*val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
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break;
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case IRQCHIP_STATE_ACTIVE:
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*val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
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break;
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case IRQCHIP_STATE_MASKED:
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*val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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void __iomem *base = gic_dist_base(d);
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unsigned int gicirq = gic_irq(d);
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/* Interrupt configuration for SGIs can't be changed */
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if (gicirq < 16)
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return -EINVAL;
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/* SPIs have restrictions on the supported types */
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if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
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type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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return gic_configure_irq(gicirq, type, base, NULL);
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}
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#ifdef CONFIG_SMP
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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bool force)
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{
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
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unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
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u32 val, mask, bit;
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unsigned long flags;
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if (!force)
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cpu = cpumask_any_and(mask_val, cpu_online_mask);
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else
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cpu = cpumask_first(mask_val);
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if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
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return -EINVAL;
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raw_spin_lock_irqsave(&irq_controller_lock, flags);
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mask = 0xff << shift;
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bit = gic_cpu_map[cpu] << shift;
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val = readl_relaxed(reg) & ~mask;
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writel_relaxed(val | bit, reg);
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raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
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return IRQ_SET_MASK_OK;
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}
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#endif
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static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
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{
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u32 irqstat, irqnr;
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struct gic_chip_data *gic = &gic_data[0];
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void __iomem *cpu_base = gic_data_cpu_base(gic);
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do {
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irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
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irqnr = irqstat & GICC_IAR_INT_ID_MASK;
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if (likely(irqnr > 15 && irqnr < 1021)) {
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handle_domain_irq(gic->domain, irqnr, regs);
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continue;
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}
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if (irqnr < 16) {
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writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
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#ifdef CONFIG_SMP
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handle_IPI(irqnr, regs);
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#endif
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continue;
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}
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break;
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} while (1);
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}
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static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct gic_chip_data *chip_data = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned int cascade_irq, gic_irq;
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unsigned long status;
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chained_irq_enter(chip, desc);
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raw_spin_lock(&irq_controller_lock);
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status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
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raw_spin_unlock(&irq_controller_lock);
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gic_irq = (status & GICC_IAR_INT_ID_MASK);
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if (gic_irq == GICC_INT_SPURIOUS)
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goto out;
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cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
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if (unlikely(gic_irq < 32 || gic_irq > 1020))
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handle_bad_irq(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip gic_chip = {
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.name = "GIC",
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.irq_mask = gic_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoi_irq,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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};
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void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
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{
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
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BUG();
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irq_set_chained_handler(irq, gic_handle_cascade_irq);
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}
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static u8 gic_get_cpumask(struct gic_chip_data *gic)
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{
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void __iomem *base = gic_data_dist_base(gic);
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u32 mask, i;
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for (i = mask = 0; i < 32; i += 4) {
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mask = readl_relaxed(base + GIC_DIST_TARGET + i);
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mask |= mask >> 16;
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mask |= mask >> 8;
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if (mask)
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break;
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}
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if (!mask && num_possible_cpus() > 1)
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pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
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return mask;
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}
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static void gic_cpu_if_up(void)
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{
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void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
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u32 bypass = 0;
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/*
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* Preserve bypass disable bits to be written back later
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*/
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bypass = readl(cpu_base + GIC_CPU_CTRL);
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bypass &= GICC_DIS_BYPASS_MASK;
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writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
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}
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static void __init gic_dist_init(struct gic_chip_data *gic)
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{
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unsigned int i;
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u32 cpumask;
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unsigned int gic_irqs = gic->gic_irqs;
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void __iomem *base = gic_data_dist_base(gic);
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writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
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/*
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* Set all global interrupts to this CPU only.
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*/
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cpumask = gic_get_cpumask(gic);
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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for (i = 32; i < gic_irqs; i += 4)
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writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
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gic_dist_config(base, gic_irqs, NULL);
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writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
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}
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static void gic_cpu_init(struct gic_chip_data *gic)
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{
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void __iomem *dist_base = gic_data_dist_base(gic);
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void __iomem *base = gic_data_cpu_base(gic);
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unsigned int cpu_mask, cpu = smp_processor_id();
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int i;
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/*
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* Get what the GIC says our CPU mask is.
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*/
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BUG_ON(cpu >= NR_GIC_CPU_IF);
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cpu_mask = gic_get_cpumask(gic);
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gic_cpu_map[cpu] = cpu_mask;
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/*
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* Clear our mask from the other map entries in case they're
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* still undefined.
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*/
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for (i = 0; i < NR_GIC_CPU_IF; i++)
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if (i != cpu)
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gic_cpu_map[i] &= ~cpu_mask;
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gic_cpu_config(dist_base, NULL);
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writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
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gic_cpu_if_up();
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}
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void gic_cpu_if_down(void)
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{
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void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
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u32 val = 0;
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val = readl(cpu_base + GIC_CPU_CTRL);
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val &= ~GICC_ENABLE;
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writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
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}
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#ifdef CONFIG_CPU_PM
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/*
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* Saves the GIC distributor registers during suspend or idle. Must be called
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* with interrupts disabled but before powering down the GIC. After calling
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* this function, no interrupts will be delivered by the GIC, and another
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* platform-specific wakeup source must be enabled.
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*/
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static void gic_dist_save(unsigned int gic_nr)
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{
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unsigned int gic_irqs;
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void __iomem *dist_base;
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int i;
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if (gic_nr >= MAX_GIC_NR)
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BUG();
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gic_irqs = gic_data[gic_nr].gic_irqs;
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dist_base = gic_data_dist_base(&gic_data[gic_nr]);
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if (!dist_base)
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return;
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
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gic_data[gic_nr].saved_spi_conf[i] =
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readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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gic_data[gic_nr].saved_spi_target[i] =
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readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
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gic_data[gic_nr].saved_spi_enable[i] =
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readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
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}
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/*
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* Restores the GIC distributor registers during resume or when coming out of
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* idle. Must be called before enabling interrupts. If a level interrupt
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* that occured while the GIC was suspended is still present, it will be
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* handled normally, but any edge interrupts that occured will not be seen by
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* the GIC and need to be handled by the platform-specific wakeup source.
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*/
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static void gic_dist_restore(unsigned int gic_nr)
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{
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unsigned int gic_irqs;
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unsigned int i;
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void __iomem *dist_base;
|
|
|
|
if (gic_nr >= MAX_GIC_NR)
|
|
BUG();
|
|
|
|
gic_irqs = gic_data[gic_nr].gic_irqs;
|
|
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
|
|
|
if (!dist_base)
|
|
return;
|
|
|
|
writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
|
|
writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
|
|
dist_base + GIC_DIST_CONFIG + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
|
|
writel_relaxed(GICD_INT_DEF_PRI_X4,
|
|
dist_base + GIC_DIST_PRI + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
|
|
writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
|
|
dist_base + GIC_DIST_TARGET + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
|
|
writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
|
|
dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
|
|
|
writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
|
|
}
|
|
|
|
static void gic_cpu_save(unsigned int gic_nr)
|
|
{
|
|
int i;
|
|
u32 *ptr;
|
|
void __iomem *dist_base;
|
|
void __iomem *cpu_base;
|
|
|
|
if (gic_nr >= MAX_GIC_NR)
|
|
BUG();
|
|
|
|
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
|
cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
|
|
|
|
if (!dist_base || !cpu_base)
|
|
return;
|
|
|
|
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
|
|
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
|
|
ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
|
|
|
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
|
|
for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
|
|
ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
|
|
|
|
}
|
|
|
|
static void gic_cpu_restore(unsigned int gic_nr)
|
|
{
|
|
int i;
|
|
u32 *ptr;
|
|
void __iomem *dist_base;
|
|
void __iomem *cpu_base;
|
|
|
|
if (gic_nr >= MAX_GIC_NR)
|
|
BUG();
|
|
|
|
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
|
cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
|
|
|
|
if (!dist_base || !cpu_base)
|
|
return;
|
|
|
|
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
|
|
for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
|
|
writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
|
|
|
|
ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
|
|
for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
|
|
writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
|
|
|
|
for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
|
|
writel_relaxed(GICD_INT_DEF_PRI_X4,
|
|
dist_base + GIC_DIST_PRI + i * 4);
|
|
|
|
writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
|
|
gic_cpu_if_up();
|
|
}
|
|
|
|
static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MAX_GIC_NR; i++) {
|
|
#ifdef CONFIG_GIC_NON_BANKED
|
|
/* Skip over unused GICs */
|
|
if (!gic_data[i].get_base)
|
|
continue;
|
|
#endif
|
|
switch (cmd) {
|
|
case CPU_PM_ENTER:
|
|
gic_cpu_save(i);
|
|
break;
|
|
case CPU_PM_ENTER_FAILED:
|
|
case CPU_PM_EXIT:
|
|
gic_cpu_restore(i);
|
|
break;
|
|
case CPU_CLUSTER_PM_ENTER:
|
|
gic_dist_save(i);
|
|
break;
|
|
case CPU_CLUSTER_PM_ENTER_FAILED:
|
|
case CPU_CLUSTER_PM_EXIT:
|
|
gic_dist_restore(i);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block gic_notifier_block = {
|
|
.notifier_call = gic_notifier,
|
|
};
|
|
|
|
static void __init gic_pm_init(struct gic_chip_data *gic)
|
|
{
|
|
gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
|
|
sizeof(u32));
|
|
BUG_ON(!gic->saved_ppi_enable);
|
|
|
|
gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
|
|
sizeof(u32));
|
|
BUG_ON(!gic->saved_ppi_conf);
|
|
|
|
if (gic == &gic_data[0])
|
|
cpu_pm_register_notifier(&gic_notifier_block);
|
|
}
|
|
#else
|
|
static void __init gic_pm_init(struct gic_chip_data *gic)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMP
|
|
static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
|
|
{
|
|
int cpu;
|
|
unsigned long flags, map = 0;
|
|
|
|
raw_spin_lock_irqsave(&irq_controller_lock, flags);
|
|
|
|
/* Convert our logical CPU mask into a physical one. */
|
|
for_each_cpu(cpu, mask)
|
|
map |= gic_cpu_map[cpu];
|
|
|
|
/*
|
|
* Ensure that stores to Normal memory are visible to the
|
|
* other CPUs before they observe us issuing the IPI.
|
|
*/
|
|
dmb(ishst);
|
|
|
|
/* this always happens on GIC0 */
|
|
writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
|
|
|
|
raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_BL_SWITCHER
|
|
/*
|
|
* gic_send_sgi - send a SGI directly to given CPU interface number
|
|
*
|
|
* cpu_id: the ID for the destination CPU interface
|
|
* irq: the IPI number to send a SGI for
|
|
*/
|
|
void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
|
|
{
|
|
BUG_ON(cpu_id >= NR_GIC_CPU_IF);
|
|
cpu_id = 1 << cpu_id;
|
|
/* this always happens on GIC0 */
|
|
writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
|
|
}
|
|
|
|
/*
|
|
* gic_get_cpu_id - get the CPU interface ID for the specified CPU
|
|
*
|
|
* @cpu: the logical CPU number to get the GIC ID for.
|
|
*
|
|
* Return the CPU interface ID for the given logical CPU number,
|
|
* or -1 if the CPU number is too large or the interface ID is
|
|
* unknown (more than one bit set).
|
|
*/
|
|
int gic_get_cpu_id(unsigned int cpu)
|
|
{
|
|
unsigned int cpu_bit;
|
|
|
|
if (cpu >= NR_GIC_CPU_IF)
|
|
return -1;
|
|
cpu_bit = gic_cpu_map[cpu];
|
|
if (cpu_bit & (cpu_bit - 1))
|
|
return -1;
|
|
return __ffs(cpu_bit);
|
|
}
|
|
|
|
/*
|
|
* gic_migrate_target - migrate IRQs to another CPU interface
|
|
*
|
|
* @new_cpu_id: the CPU target ID to migrate IRQs to
|
|
*
|
|
* Migrate all peripheral interrupts with a target matching the current CPU
|
|
* to the interface corresponding to @new_cpu_id. The CPU interface mapping
|
|
* is also updated. Targets to other CPU interfaces are unchanged.
|
|
* This must be called with IRQs locally disabled.
|
|
*/
|
|
void gic_migrate_target(unsigned int new_cpu_id)
|
|
{
|
|
unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
|
|
void __iomem *dist_base;
|
|
int i, ror_val, cpu = smp_processor_id();
|
|
u32 val, cur_target_mask, active_mask;
|
|
|
|
if (gic_nr >= MAX_GIC_NR)
|
|
BUG();
|
|
|
|
dist_base = gic_data_dist_base(&gic_data[gic_nr]);
|
|
if (!dist_base)
|
|
return;
|
|
gic_irqs = gic_data[gic_nr].gic_irqs;
|
|
|
|
cur_cpu_id = __ffs(gic_cpu_map[cpu]);
|
|
cur_target_mask = 0x01010101 << cur_cpu_id;
|
|
ror_val = (cur_cpu_id - new_cpu_id) & 31;
|
|
|
|
raw_spin_lock(&irq_controller_lock);
|
|
|
|
/* Update the target interface for this logical CPU */
|
|
gic_cpu_map[cpu] = 1 << new_cpu_id;
|
|
|
|
/*
|
|
* Find all the peripheral interrupts targetting the current
|
|
* CPU interface and migrate them to the new CPU interface.
|
|
* We skip DIST_TARGET 0 to 7 as they are read-only.
|
|
*/
|
|
for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
|
|
val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
|
|
active_mask = val & cur_target_mask;
|
|
if (active_mask) {
|
|
val &= ~active_mask;
|
|
val |= ror32(active_mask, ror_val);
|
|
writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
|
|
}
|
|
}
|
|
|
|
raw_spin_unlock(&irq_controller_lock);
|
|
|
|
/*
|
|
* Now let's migrate and clear any potential SGIs that might be
|
|
* pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
|
|
* is a banked register, we can only forward the SGI using
|
|
* GIC_DIST_SOFTINT. The original SGI source is lost but Linux
|
|
* doesn't use that information anyway.
|
|
*
|
|
* For the same reason we do not adjust SGI source information
|
|
* for previously sent SGIs by us to other CPUs either.
|
|
*/
|
|
for (i = 0; i < 16; i += 4) {
|
|
int j;
|
|
val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
|
|
if (!val)
|
|
continue;
|
|
writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
|
|
for (j = i; j < i + 4; j++) {
|
|
if (val & 0xff)
|
|
writel_relaxed((1 << (new_cpu_id + 16)) | j,
|
|
dist_base + GIC_DIST_SOFTINT);
|
|
val >>= 8;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* gic_get_sgir_physaddr - get the physical address for the SGI register
|
|
*
|
|
* REturn the physical address of the SGI register to be used
|
|
* by some early assembly code when the kernel is not yet available.
|
|
*/
|
|
static unsigned long gic_dist_physaddr;
|
|
|
|
unsigned long gic_get_sgir_physaddr(void)
|
|
{
|
|
if (!gic_dist_physaddr)
|
|
return 0;
|
|
return gic_dist_physaddr + GIC_DIST_SOFTINT;
|
|
}
|
|
|
|
void __init gic_init_physaddr(struct device_node *node)
|
|
{
|
|
struct resource res;
|
|
if (of_address_to_resource(node, 0, &res) == 0) {
|
|
gic_dist_physaddr = res.start;
|
|
pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
|
|
}
|
|
}
|
|
|
|
#else
|
|
#define gic_init_physaddr(node) do { } while (0)
|
|
#endif
|
|
|
|
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
if (hw < 32) {
|
|
irq_set_percpu_devid(irq);
|
|
irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
|
handle_percpu_devid_irq, NULL, NULL);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
|
|
} else {
|
|
irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
|
|
handle_fasteoi_irq, NULL, NULL);
|
|
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
|
|
{
|
|
}
|
|
|
|
static int gic_irq_domain_xlate(struct irq_domain *d,
|
|
struct device_node *controller,
|
|
const u32 *intspec, unsigned int intsize,
|
|
unsigned long *out_hwirq, unsigned int *out_type)
|
|
{
|
|
unsigned long ret = 0;
|
|
|
|
if (d->of_node != controller)
|
|
return -EINVAL;
|
|
if (intsize < 3)
|
|
return -EINVAL;
|
|
|
|
/* Get the interrupt number and add 16 to skip over SGIs */
|
|
*out_hwirq = intspec[1] + 16;
|
|
|
|
/* For SPIs, we need to add 16 more to get the GIC irq ID number */
|
|
if (!intspec[0])
|
|
*out_hwirq += 16;
|
|
|
|
*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
|
|
void *hcpu)
|
|
{
|
|
if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
|
|
gic_cpu_init(&gic_data[0]);
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
/*
|
|
* Notifier for enabling the GIC CPU interface. Set an arbitrarily high
|
|
* priority because the GIC needs to be up before the ARM generic timers.
|
|
*/
|
|
static struct notifier_block gic_cpu_notifier = {
|
|
.notifier_call = gic_secondary_init,
|
|
.priority = 100,
|
|
};
|
|
#endif
|
|
|
|
static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
|
|
unsigned int nr_irqs, void *arg)
|
|
{
|
|
int i, ret;
|
|
irq_hw_number_t hwirq;
|
|
unsigned int type = IRQ_TYPE_NONE;
|
|
struct of_phandle_args *irq_data = arg;
|
|
|
|
ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
|
|
irq_data->args_count, &hwirq, &type);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
gic_irq_domain_map(domain, virq + i, hwirq + i);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
|
|
.xlate = gic_irq_domain_xlate,
|
|
.alloc = gic_irq_domain_alloc,
|
|
.free = irq_domain_free_irqs_top,
|
|
};
|
|
|
|
static const struct irq_domain_ops gic_irq_domain_ops = {
|
|
.map = gic_irq_domain_map,
|
|
.unmap = gic_irq_domain_unmap,
|
|
.xlate = gic_irq_domain_xlate,
|
|
};
|
|
|
|
void gic_set_irqchip_flags(unsigned long flags)
|
|
{
|
|
gic_chip.flags |= flags;
|
|
}
|
|
|
|
void __init gic_init_bases(unsigned int gic_nr, int irq_start,
|
|
void __iomem *dist_base, void __iomem *cpu_base,
|
|
u32 percpu_offset, struct device_node *node)
|
|
{
|
|
irq_hw_number_t hwirq_base;
|
|
struct gic_chip_data *gic;
|
|
int gic_irqs, irq_base, i;
|
|
|
|
BUG_ON(gic_nr >= MAX_GIC_NR);
|
|
|
|
gic = &gic_data[gic_nr];
|
|
#ifdef CONFIG_GIC_NON_BANKED
|
|
if (percpu_offset) { /* Frankein-GIC without banked registers... */
|
|
unsigned int cpu;
|
|
|
|
gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
|
|
gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
|
|
if (WARN_ON(!gic->dist_base.percpu_base ||
|
|
!gic->cpu_base.percpu_base)) {
|
|
free_percpu(gic->dist_base.percpu_base);
|
|
free_percpu(gic->cpu_base.percpu_base);
|
|
return;
|
|
}
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
u32 mpidr = cpu_logical_map(cpu);
|
|
u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
|
unsigned long offset = percpu_offset * core_id;
|
|
*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
|
|
*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
|
|
}
|
|
|
|
gic_set_base_accessor(gic, gic_get_percpu_base);
|
|
} else
|
|
#endif
|
|
{ /* Normal, sane GIC... */
|
|
WARN(percpu_offset,
|
|
"GIC_NON_BANKED not enabled, ignoring %08x offset!",
|
|
percpu_offset);
|
|
gic->dist_base.common_base = dist_base;
|
|
gic->cpu_base.common_base = cpu_base;
|
|
gic_set_base_accessor(gic, gic_get_common_base);
|
|
}
|
|
|
|
/*
|
|
* Initialize the CPU interface map to all CPUs.
|
|
* It will be refined as each CPU probes its ID.
|
|
*/
|
|
for (i = 0; i < NR_GIC_CPU_IF; i++)
|
|
gic_cpu_map[i] = 0xff;
|
|
|
|
/*
|
|
* Find out how many interrupts are supported.
|
|
* The GIC only supports up to 1020 interrupt sources.
|
|
*/
|
|
gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
|
|
gic_irqs = (gic_irqs + 1) * 32;
|
|
if (gic_irqs > 1020)
|
|
gic_irqs = 1020;
|
|
gic->gic_irqs = gic_irqs;
|
|
|
|
if (node) { /* DT case */
|
|
gic->domain = irq_domain_add_linear(node, gic_irqs,
|
|
&gic_irq_domain_hierarchy_ops,
|
|
gic);
|
|
} else { /* Non-DT case */
|
|
/*
|
|
* For primary GICs, skip over SGIs.
|
|
* For secondary GICs, skip over PPIs, too.
|
|
*/
|
|
if (gic_nr == 0 && (irq_start & 31) > 0) {
|
|
hwirq_base = 16;
|
|
if (irq_start != -1)
|
|
irq_start = (irq_start & ~31) + 16;
|
|
} else {
|
|
hwirq_base = 32;
|
|
}
|
|
|
|
gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
|
|
|
|
irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
|
|
numa_node_id());
|
|
if (IS_ERR_VALUE(irq_base)) {
|
|
WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
|
|
irq_start);
|
|
irq_base = irq_start;
|
|
}
|
|
|
|
gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
|
|
hwirq_base, &gic_irq_domain_ops, gic);
|
|
}
|
|
|
|
if (WARN_ON(!gic->domain))
|
|
return;
|
|
|
|
if (gic_nr == 0) {
|
|
#ifdef CONFIG_SMP
|
|
set_smp_cross_call(gic_raise_softirq);
|
|
register_cpu_notifier(&gic_cpu_notifier);
|
|
#endif
|
|
set_handle_irq(gic_handle_irq);
|
|
}
|
|
|
|
gic_dist_init(gic);
|
|
gic_cpu_init(gic);
|
|
gic_pm_init(gic);
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static int gic_cnt __initdata;
|
|
|
|
static int __init
|
|
gic_of_init(struct device_node *node, struct device_node *parent)
|
|
{
|
|
void __iomem *cpu_base;
|
|
void __iomem *dist_base;
|
|
u32 percpu_offset;
|
|
int irq;
|
|
|
|
if (WARN_ON(!node))
|
|
return -ENODEV;
|
|
|
|
dist_base = of_iomap(node, 0);
|
|
WARN(!dist_base, "unable to map gic dist registers\n");
|
|
|
|
cpu_base = of_iomap(node, 1);
|
|
WARN(!cpu_base, "unable to map gic cpu registers\n");
|
|
|
|
if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
|
|
percpu_offset = 0;
|
|
|
|
gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
|
|
if (!gic_cnt)
|
|
gic_init_physaddr(node);
|
|
|
|
if (parent) {
|
|
irq = irq_of_parse_and_map(node, 0);
|
|
gic_cascade_irq(gic_cnt, irq);
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
|
|
gicv2m_of_init(node, gic_data[gic_cnt].domain);
|
|
|
|
gic_cnt++;
|
|
return 0;
|
|
}
|
|
IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
|
|
IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
|
|
IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
|
|
IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
|
|
IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
|
|
IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
|
|
IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
|
|
IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ACPI
|
|
static phys_addr_t dist_phy_base, cpu_phy_base __initdata;
|
|
|
|
static int __init
|
|
gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
|
|
const unsigned long end)
|
|
{
|
|
struct acpi_madt_generic_interrupt *processor;
|
|
phys_addr_t gic_cpu_base;
|
|
static int cpu_base_assigned;
|
|
|
|
processor = (struct acpi_madt_generic_interrupt *)header;
|
|
|
|
if (BAD_MADT_ENTRY(processor, end))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* There is no support for non-banked GICv1/2 register in ACPI spec.
|
|
* All CPU interface addresses have to be the same.
|
|
*/
|
|
gic_cpu_base = processor->base_address;
|
|
if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
|
|
return -EINVAL;
|
|
|
|
cpu_phy_base = gic_cpu_base;
|
|
cpu_base_assigned = 1;
|
|
return 0;
|
|
}
|
|
|
|
static int __init
|
|
gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
|
|
const unsigned long end)
|
|
{
|
|
struct acpi_madt_generic_distributor *dist;
|
|
|
|
dist = (struct acpi_madt_generic_distributor *)header;
|
|
|
|
if (BAD_MADT_ENTRY(dist, end))
|
|
return -EINVAL;
|
|
|
|
dist_phy_base = dist->base_address;
|
|
return 0;
|
|
}
|
|
|
|
int __init
|
|
gic_v2_acpi_init(struct acpi_table_header *table)
|
|
{
|
|
void __iomem *cpu_base, *dist_base;
|
|
int count;
|
|
|
|
/* Collect CPU base addresses */
|
|
count = acpi_parse_entries(ACPI_SIG_MADT,
|
|
sizeof(struct acpi_table_madt),
|
|
gic_acpi_parse_madt_cpu, table,
|
|
ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
|
|
if (count <= 0) {
|
|
pr_err("No valid GICC entries exist\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Find distributor base address. We expect one distributor entry since
|
|
* ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade.
|
|
*/
|
|
count = acpi_parse_entries(ACPI_SIG_MADT,
|
|
sizeof(struct acpi_table_madt),
|
|
gic_acpi_parse_madt_distributor, table,
|
|
ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
|
|
if (count <= 0) {
|
|
pr_err("No valid GICD entries exist\n");
|
|
return -EINVAL;
|
|
} else if (count > 1) {
|
|
pr_err("More than one GICD entry detected\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
|
|
if (!cpu_base) {
|
|
pr_err("Unable to map GICC registers\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE);
|
|
if (!dist_base) {
|
|
pr_err("Unable to map GICD registers\n");
|
|
iounmap(cpu_base);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/*
|
|
* Initialize zero GIC instance (no multi-GIC support). Also, set GIC
|
|
* as default IRQ domain to allow for GSI registration and GSI to IRQ
|
|
* number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
|
|
*/
|
|
gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
|
|
irq_set_default_host(gic_data[0].domain);
|
|
|
|
acpi_irq_model = ACPI_IRQ_MODEL_GIC;
|
|
return 0;
|
|
}
|
|
#endif
|