46 lines
1.2 KiB
Plaintext
46 lines
1.2 KiB
Plaintext
Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
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This binding represents the on-chip eFuse OTP controller found on
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i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ and i.MX6SLL SoCs.
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Required properties:
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- compatible: should be one of
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"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
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"fsl,imx6sl-ocotp" (i.MX6SL), or
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"fsl,imx6sx-ocotp" (i.MX6SX),
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"fsl,imx6ul-ocotp" (i.MX6UL),
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"fsl,imx6ull-ocotp" (i.MX6ULL/ULZ),
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"fsl,imx7d-ocotp" (i.MX7D/S),
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"fsl,imx6sll-ocotp" (i.MX6SLL),
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"fsl,imx7ulp-ocotp" (i.MX7ULP),
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followed by "syscon".
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- #address-cells : Should be 1
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- #size-cells : Should be 1
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- reg: Should contain the register base and length.
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- clocks: Should contain a phandle pointing to the gated peripheral clock.
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Optional properties:
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- read-only: disable write access
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Optional Child nodes:
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- Data cells of ocotp:
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Detailed bindings are described in bindings/nvmem/nvmem.txt
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Example:
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ocotp: ocotp@21bc000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,imx6sx-ocotp", "syscon";
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reg = <0x021bc000 0x4000>;
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clocks = <&clks IMX6SX_CLK_OCOTP>;
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tempmon_calib: calib@38 {
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reg = <0x38 4>;
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};
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tempmon_temp_grade: temp-grade@20 {
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reg = <0x20 4>;
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};
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};
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