62b0194368
The RISC-V ISA defines a per-hart real-time clock and timer, which is present on all systems. The clock is accessed via the 'rdtime' pseudo-instruction (which reads a CSR), and the timer is set via an SBI call. Contains various improvements from Atish Patra <atish.patra@wdc.com>. Signed-off-by: Dmitriy Cherkasov <dmitriy@oss-tech.org> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> [hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(), minor cleanups, merged hotplug cpu support and other improvements from Atish] Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
34 lines
990 B
C
34 lines
990 B
C
/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clocksource.h>
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#include <linux/delay.h>
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#include <asm/sbi.h>
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unsigned long riscv_timebase;
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void __init time_init(void)
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{
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struct device_node *cpu;
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u32 prop;
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cpu = of_find_node_by_path("/cpus");
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if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop))
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panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n");
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riscv_timebase = prop;
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lpj_fine = riscv_timebase / HZ;
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timer_probe();
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}
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