![Greg Kroah-Hartman](/assets/img/avatar_default.png)
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
807 lines
19 KiB
C
807 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* General Purpose functions for the global management of the
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* Communication Processor Module.
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* Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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* The amount of space available is platform dependent. On the
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* MBX, the EPPC software loads additional microcode into the
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* communication processor, and uses some of the DP ram for this
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* purpose. Current, the first 512 bytes and the last 256 bytes of
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* memory are used. Right now I am conservative and only use the
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* memory that can never be used for microcode. If there are
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* applications that require more DP ram, we can expand the boundaries
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* but then we have to be careful of any downloaded microcode.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/dma-mapping.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/8xx_immap.h>
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#include <asm/cpm1.h>
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#include <asm/io.h>
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#include <asm/tlbflush.h>
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#include <asm/rheap.h>
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#include <asm/prom.h>
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#include <asm/cpm.h>
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#include <asm/fs_pd.h>
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#ifdef CONFIG_8xx_GPIO
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#include <linux/of_gpio.h>
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#endif
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#define CPM_MAP_SIZE (0x4000)
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cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
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immap_t __iomem *mpc8xx_immr;
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static cpic8xx_t __iomem *cpic_reg;
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static struct irq_domain *cpm_pic_host;
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static void cpm_mask_irq(struct irq_data *d)
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{
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unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
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clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
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}
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static void cpm_unmask_irq(struct irq_data *d)
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{
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unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
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setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
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}
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static void cpm_end_irq(struct irq_data *d)
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{
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unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
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out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
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}
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static struct irq_chip cpm_pic = {
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.name = "CPM PIC",
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.irq_mask = cpm_mask_irq,
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.irq_unmask = cpm_unmask_irq,
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.irq_eoi = cpm_end_irq,
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};
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int cpm_get_irq(void)
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{
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int cpm_vec;
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/* Get the vector by setting the ACK bit and then reading
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* the register.
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*/
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out_be16(&cpic_reg->cpic_civr, 1);
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cpm_vec = in_be16(&cpic_reg->cpic_civr);
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cpm_vec >>= 11;
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return irq_linear_revmap(cpm_pic_host, cpm_vec);
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}
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static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
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return 0;
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}
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/* The CPM can generate the error interrupt when there is a race condition
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* between generating and masking interrupts. All we have to do is ACK it
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* and return. This is a no-op function so we don't need any special
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* tests in the interrupt handler.
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*/
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static irqreturn_t cpm_error_interrupt(int irq, void *dev)
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{
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return IRQ_HANDLED;
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}
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static struct irqaction cpm_error_irqaction = {
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.handler = cpm_error_interrupt,
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.flags = IRQF_NO_THREAD,
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.name = "error",
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};
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static const struct irq_domain_ops cpm_pic_host_ops = {
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.map = cpm_pic_host_map,
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};
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unsigned int cpm_pic_init(void)
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{
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struct device_node *np = NULL;
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struct resource res;
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unsigned int sirq = 0, hwirq, eirq;
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int ret;
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pr_debug("cpm_pic_init\n");
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
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if (np == NULL)
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np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
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if (np == NULL) {
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printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
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return sirq;
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}
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ret = of_address_to_resource(np, 0, &res);
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if (ret)
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goto end;
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cpic_reg = ioremap(res.start, resource_size(&res));
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if (cpic_reg == NULL)
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goto end;
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sirq = irq_of_parse_and_map(np, 0);
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if (!sirq)
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goto end;
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/* Initialize the CPM interrupt controller. */
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hwirq = (unsigned int)virq_to_hw(sirq);
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out_be32(&cpic_reg->cpic_cicr,
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(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
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((hwirq/2) << 13) | CICR_HP_MASK);
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out_be32(&cpic_reg->cpic_cimr, 0);
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cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
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if (cpm_pic_host == NULL) {
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printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
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sirq = 0;
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goto end;
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}
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/* Install our own error handler. */
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
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if (np == NULL)
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np = of_find_node_by_type(NULL, "cpm");
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if (np == NULL) {
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printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
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goto end;
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}
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eirq = irq_of_parse_and_map(np, 0);
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if (!eirq)
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goto end;
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if (setup_irq(eirq, &cpm_error_irqaction))
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printk(KERN_ERR "Could not allocate CPM error IRQ!");
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setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
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end:
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of_node_put(np);
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return sirq;
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}
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void __init cpm_reset(void)
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{
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sysconf8xx_t __iomem *siu_conf;
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mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
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if (!mpc8xx_immr) {
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printk(KERN_CRIT "Could not map IMMR\n");
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return;
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}
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cpmp = &mpc8xx_immr->im_cpm;
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#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
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/* Perform a reset.
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*/
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out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
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/* Wait for it.
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*/
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while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
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#endif
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#ifdef CONFIG_UCODE_PATCH
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cpm_load_patch(cpmp);
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#endif
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/* Set SDMA Bus Request priority 5.
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* On 860T, this also enables FEC priority 6. I am not sure
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* this is what we really want for some applications, but the
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* manual recommends it.
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* Bit 25, FAM can also be set to use FEC aggressive mode (860T).
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*/
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siu_conf = immr_map(im_siu_conf);
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if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
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out_be32(&siu_conf->sc_sdcr, 0x40);
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else
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out_be32(&siu_conf->sc_sdcr, 1);
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immr_unmap(siu_conf);
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}
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static DEFINE_SPINLOCK(cmd_lock);
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#define MAX_CR_CMD_LOOPS 10000
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int cpm_command(u32 command, u8 opcode)
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{
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int i, ret;
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unsigned long flags;
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if (command & 0xffffff0f)
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return -EINVAL;
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spin_lock_irqsave(&cmd_lock, flags);
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ret = 0;
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out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
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for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
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if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
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goto out;
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printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
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ret = -EIO;
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out:
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spin_unlock_irqrestore(&cmd_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(cpm_command);
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/* Set a baud rate generator. This needs lots of work. There are
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* four BRGs, any of which can be wired to any channel.
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* The internal baud rate clock is the system clock divided by 16.
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* This assumes the baudrate is 16x oversampled by the uart.
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*/
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#define BRG_INT_CLK (get_brgfreq())
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#define BRG_UART_CLK (BRG_INT_CLK/16)
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#define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16)
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void
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cpm_setbrg(uint brg, uint rate)
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{
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u32 __iomem *bp;
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/* This is good enough to get SMCs running.....
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*/
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bp = &cpmp->cp_brgc1;
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bp += brg;
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/* The BRG has a 12-bit counter. For really slow baud rates (or
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* really fast processors), we may have to further divide by 16.
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*/
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if (((BRG_UART_CLK / rate) - 1) < 4096)
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out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
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else
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out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
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CPM_BRG_EN | CPM_BRG_DIV16);
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}
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struct cpm_ioport16 {
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__be16 dir, par, odr_sor, dat, intr;
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__be16 res[3];
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};
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struct cpm_ioport32b {
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__be32 dir, par, odr, dat;
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};
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struct cpm_ioport32e {
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__be32 dir, par, sor, odr, dat;
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};
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static void cpm1_set_pin32(int port, int pin, int flags)
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{
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struct cpm_ioport32e __iomem *iop;
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pin = 1 << (31 - pin);
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if (port == CPM_PORTB)
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iop = (struct cpm_ioport32e __iomem *)
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&mpc8xx_immr->im_cpm.cp_pbdir;
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else
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iop = (struct cpm_ioport32e __iomem *)
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&mpc8xx_immr->im_cpm.cp_pedir;
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if (flags & CPM_PIN_OUTPUT)
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setbits32(&iop->dir, pin);
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else
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clrbits32(&iop->dir, pin);
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if (!(flags & CPM_PIN_GPIO))
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setbits32(&iop->par, pin);
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else
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clrbits32(&iop->par, pin);
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if (port == CPM_PORTB) {
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if (flags & CPM_PIN_OPENDRAIN)
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setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
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else
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clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
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}
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if (port == CPM_PORTE) {
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if (flags & CPM_PIN_SECONDARY)
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setbits32(&iop->sor, pin);
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else
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clrbits32(&iop->sor, pin);
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if (flags & CPM_PIN_OPENDRAIN)
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setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
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else
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clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
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}
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}
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static void cpm1_set_pin16(int port, int pin, int flags)
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{
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struct cpm_ioport16 __iomem *iop =
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(struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
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pin = 1 << (15 - pin);
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if (port != 0)
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iop += port - 1;
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if (flags & CPM_PIN_OUTPUT)
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setbits16(&iop->dir, pin);
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else
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clrbits16(&iop->dir, pin);
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if (!(flags & CPM_PIN_GPIO))
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setbits16(&iop->par, pin);
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else
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clrbits16(&iop->par, pin);
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if (port == CPM_PORTA) {
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if (flags & CPM_PIN_OPENDRAIN)
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setbits16(&iop->odr_sor, pin);
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else
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clrbits16(&iop->odr_sor, pin);
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}
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if (port == CPM_PORTC) {
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if (flags & CPM_PIN_SECONDARY)
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setbits16(&iop->odr_sor, pin);
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else
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clrbits16(&iop->odr_sor, pin);
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if (flags & CPM_PIN_FALLEDGE)
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setbits16(&iop->intr, pin);
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else
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clrbits16(&iop->intr, pin);
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}
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}
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void cpm1_set_pin(enum cpm_port port, int pin, int flags)
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{
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if (port == CPM_PORTB || port == CPM_PORTE)
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cpm1_set_pin32(port, pin, flags);
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else
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cpm1_set_pin16(port, pin, flags);
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}
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int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
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{
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int shift;
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int i, bits = 0;
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u32 __iomem *reg;
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u32 mask = 7;
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u8 clk_map[][3] = {
|
|
{CPM_CLK_SCC1, CPM_BRG1, 0},
|
|
{CPM_CLK_SCC1, CPM_BRG2, 1},
|
|
{CPM_CLK_SCC1, CPM_BRG3, 2},
|
|
{CPM_CLK_SCC1, CPM_BRG4, 3},
|
|
{CPM_CLK_SCC1, CPM_CLK1, 4},
|
|
{CPM_CLK_SCC1, CPM_CLK2, 5},
|
|
{CPM_CLK_SCC1, CPM_CLK3, 6},
|
|
{CPM_CLK_SCC1, CPM_CLK4, 7},
|
|
|
|
{CPM_CLK_SCC2, CPM_BRG1, 0},
|
|
{CPM_CLK_SCC2, CPM_BRG2, 1},
|
|
{CPM_CLK_SCC2, CPM_BRG3, 2},
|
|
{CPM_CLK_SCC2, CPM_BRG4, 3},
|
|
{CPM_CLK_SCC2, CPM_CLK1, 4},
|
|
{CPM_CLK_SCC2, CPM_CLK2, 5},
|
|
{CPM_CLK_SCC2, CPM_CLK3, 6},
|
|
{CPM_CLK_SCC2, CPM_CLK4, 7},
|
|
|
|
{CPM_CLK_SCC3, CPM_BRG1, 0},
|
|
{CPM_CLK_SCC3, CPM_BRG2, 1},
|
|
{CPM_CLK_SCC3, CPM_BRG3, 2},
|
|
{CPM_CLK_SCC3, CPM_BRG4, 3},
|
|
{CPM_CLK_SCC3, CPM_CLK5, 4},
|
|
{CPM_CLK_SCC3, CPM_CLK6, 5},
|
|
{CPM_CLK_SCC3, CPM_CLK7, 6},
|
|
{CPM_CLK_SCC3, CPM_CLK8, 7},
|
|
|
|
{CPM_CLK_SCC4, CPM_BRG1, 0},
|
|
{CPM_CLK_SCC4, CPM_BRG2, 1},
|
|
{CPM_CLK_SCC4, CPM_BRG3, 2},
|
|
{CPM_CLK_SCC4, CPM_BRG4, 3},
|
|
{CPM_CLK_SCC4, CPM_CLK5, 4},
|
|
{CPM_CLK_SCC4, CPM_CLK6, 5},
|
|
{CPM_CLK_SCC4, CPM_CLK7, 6},
|
|
{CPM_CLK_SCC4, CPM_CLK8, 7},
|
|
|
|
{CPM_CLK_SMC1, CPM_BRG1, 0},
|
|
{CPM_CLK_SMC1, CPM_BRG2, 1},
|
|
{CPM_CLK_SMC1, CPM_BRG3, 2},
|
|
{CPM_CLK_SMC1, CPM_BRG4, 3},
|
|
{CPM_CLK_SMC1, CPM_CLK1, 4},
|
|
{CPM_CLK_SMC1, CPM_CLK2, 5},
|
|
{CPM_CLK_SMC1, CPM_CLK3, 6},
|
|
{CPM_CLK_SMC1, CPM_CLK4, 7},
|
|
|
|
{CPM_CLK_SMC2, CPM_BRG1, 0},
|
|
{CPM_CLK_SMC2, CPM_BRG2, 1},
|
|
{CPM_CLK_SMC2, CPM_BRG3, 2},
|
|
{CPM_CLK_SMC2, CPM_BRG4, 3},
|
|
{CPM_CLK_SMC2, CPM_CLK5, 4},
|
|
{CPM_CLK_SMC2, CPM_CLK6, 5},
|
|
{CPM_CLK_SMC2, CPM_CLK7, 6},
|
|
{CPM_CLK_SMC2, CPM_CLK8, 7},
|
|
};
|
|
|
|
switch (target) {
|
|
case CPM_CLK_SCC1:
|
|
reg = &mpc8xx_immr->im_cpm.cp_sicr;
|
|
shift = 0;
|
|
break;
|
|
|
|
case CPM_CLK_SCC2:
|
|
reg = &mpc8xx_immr->im_cpm.cp_sicr;
|
|
shift = 8;
|
|
break;
|
|
|
|
case CPM_CLK_SCC3:
|
|
reg = &mpc8xx_immr->im_cpm.cp_sicr;
|
|
shift = 16;
|
|
break;
|
|
|
|
case CPM_CLK_SCC4:
|
|
reg = &mpc8xx_immr->im_cpm.cp_sicr;
|
|
shift = 24;
|
|
break;
|
|
|
|
case CPM_CLK_SMC1:
|
|
reg = &mpc8xx_immr->im_cpm.cp_simode;
|
|
shift = 12;
|
|
break;
|
|
|
|
case CPM_CLK_SMC2:
|
|
reg = &mpc8xx_immr->im_cpm.cp_simode;
|
|
shift = 28;
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
|
|
if (clk_map[i][0] == target && clk_map[i][1] == clock) {
|
|
bits = clk_map[i][2];
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (i == ARRAY_SIZE(clk_map)) {
|
|
printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
bits <<= shift;
|
|
mask <<= shift;
|
|
|
|
if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
|
|
if (mode == CPM_CLK_RTX) {
|
|
bits |= bits << 3;
|
|
mask |= mask << 3;
|
|
} else if (mode == CPM_CLK_RX) {
|
|
bits <<= 3;
|
|
mask <<= 3;
|
|
}
|
|
}
|
|
|
|
out_be32(reg, (in_be32(reg) & ~mask) | bits);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* GPIO LIB API implementation
|
|
*/
|
|
#ifdef CONFIG_8xx_GPIO
|
|
|
|
struct cpm1_gpio16_chip {
|
|
struct of_mm_gpio_chip mm_gc;
|
|
spinlock_t lock;
|
|
|
|
/* shadowed data register to clear/set bits safely */
|
|
u16 cpdata;
|
|
|
|
/* IRQ associated with Pins when relevant */
|
|
int irq[16];
|
|
};
|
|
|
|
static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc)
|
|
{
|
|
struct cpm1_gpio16_chip *cpm1_gc =
|
|
container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc);
|
|
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
|
|
|
|
cpm1_gc->cpdata = in_be16(&iop->dat);
|
|
}
|
|
|
|
static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
|
|
u16 pin_mask;
|
|
|
|
pin_mask = 1 << (15 - gpio);
|
|
|
|
return !!(in_be16(&iop->dat) & pin_mask);
|
|
}
|
|
|
|
static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask,
|
|
int value)
|
|
{
|
|
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
|
|
|
|
if (value)
|
|
cpm1_gc->cpdata |= pin_mask;
|
|
else
|
|
cpm1_gc->cpdata &= ~pin_mask;
|
|
|
|
out_be16(&iop->dat, cpm1_gc->cpdata);
|
|
}
|
|
|
|
static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
unsigned long flags;
|
|
u16 pin_mask = 1 << (15 - gpio);
|
|
|
|
spin_lock_irqsave(&cpm1_gc->lock, flags);
|
|
|
|
__cpm1_gpio16_set(mm_gc, pin_mask, value);
|
|
|
|
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
|
|
}
|
|
|
|
static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
|
|
return cpm1_gc->irq[gpio] ? : -ENXIO;
|
|
}
|
|
|
|
static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
|
|
unsigned long flags;
|
|
u16 pin_mask = 1 << (15 - gpio);
|
|
|
|
spin_lock_irqsave(&cpm1_gc->lock, flags);
|
|
|
|
setbits16(&iop->dir, pin_mask);
|
|
__cpm1_gpio16_set(mm_gc, pin_mask, val);
|
|
|
|
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
struct cpm_ioport16 __iomem *iop = mm_gc->regs;
|
|
unsigned long flags;
|
|
u16 pin_mask = 1 << (15 - gpio);
|
|
|
|
spin_lock_irqsave(&cpm1_gc->lock, flags);
|
|
|
|
clrbits16(&iop->dir, pin_mask);
|
|
|
|
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cpm1_gpiochip_add16(struct device_node *np)
|
|
{
|
|
struct cpm1_gpio16_chip *cpm1_gc;
|
|
struct of_mm_gpio_chip *mm_gc;
|
|
struct gpio_chip *gc;
|
|
u16 mask;
|
|
|
|
cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
|
|
if (!cpm1_gc)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&cpm1_gc->lock);
|
|
|
|
if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) {
|
|
int i, j;
|
|
|
|
for (i = 0, j = 0; i < 16; i++)
|
|
if (mask & (1 << (15 - i)))
|
|
cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++);
|
|
}
|
|
|
|
mm_gc = &cpm1_gc->mm_gc;
|
|
gc = &mm_gc->gc;
|
|
|
|
mm_gc->save_regs = cpm1_gpio16_save_regs;
|
|
gc->ngpio = 16;
|
|
gc->direction_input = cpm1_gpio16_dir_in;
|
|
gc->direction_output = cpm1_gpio16_dir_out;
|
|
gc->get = cpm1_gpio16_get;
|
|
gc->set = cpm1_gpio16_set;
|
|
gc->to_irq = cpm1_gpio16_to_irq;
|
|
|
|
return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
|
|
}
|
|
|
|
struct cpm1_gpio32_chip {
|
|
struct of_mm_gpio_chip mm_gc;
|
|
spinlock_t lock;
|
|
|
|
/* shadowed data register to clear/set bits safely */
|
|
u32 cpdata;
|
|
};
|
|
|
|
static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
|
|
{
|
|
struct cpm1_gpio32_chip *cpm1_gc =
|
|
container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc);
|
|
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
|
|
|
|
cpm1_gc->cpdata = in_be32(&iop->dat);
|
|
}
|
|
|
|
static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
|
|
u32 pin_mask;
|
|
|
|
pin_mask = 1 << (31 - gpio);
|
|
|
|
return !!(in_be32(&iop->dat) & pin_mask);
|
|
}
|
|
|
|
static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
|
|
int value)
|
|
{
|
|
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
|
|
|
|
if (value)
|
|
cpm1_gc->cpdata |= pin_mask;
|
|
else
|
|
cpm1_gc->cpdata &= ~pin_mask;
|
|
|
|
out_be32(&iop->dat, cpm1_gc->cpdata);
|
|
}
|
|
|
|
static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
unsigned long flags;
|
|
u32 pin_mask = 1 << (31 - gpio);
|
|
|
|
spin_lock_irqsave(&cpm1_gc->lock, flags);
|
|
|
|
__cpm1_gpio32_set(mm_gc, pin_mask, value);
|
|
|
|
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
|
|
}
|
|
|
|
static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
|
|
unsigned long flags;
|
|
u32 pin_mask = 1 << (31 - gpio);
|
|
|
|
spin_lock_irqsave(&cpm1_gc->lock, flags);
|
|
|
|
setbits32(&iop->dir, pin_mask);
|
|
__cpm1_gpio32_set(mm_gc, pin_mask, val);
|
|
|
|
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
|
|
{
|
|
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
|
|
struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc);
|
|
struct cpm_ioport32b __iomem *iop = mm_gc->regs;
|
|
unsigned long flags;
|
|
u32 pin_mask = 1 << (31 - gpio);
|
|
|
|
spin_lock_irqsave(&cpm1_gc->lock, flags);
|
|
|
|
clrbits32(&iop->dir, pin_mask);
|
|
|
|
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cpm1_gpiochip_add32(struct device_node *np)
|
|
{
|
|
struct cpm1_gpio32_chip *cpm1_gc;
|
|
struct of_mm_gpio_chip *mm_gc;
|
|
struct gpio_chip *gc;
|
|
|
|
cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL);
|
|
if (!cpm1_gc)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&cpm1_gc->lock);
|
|
|
|
mm_gc = &cpm1_gc->mm_gc;
|
|
gc = &mm_gc->gc;
|
|
|
|
mm_gc->save_regs = cpm1_gpio32_save_regs;
|
|
gc->ngpio = 32;
|
|
gc->direction_input = cpm1_gpio32_dir_in;
|
|
gc->direction_output = cpm1_gpio32_dir_out;
|
|
gc->get = cpm1_gpio32_get;
|
|
gc->set = cpm1_gpio32_set;
|
|
|
|
return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc);
|
|
}
|
|
|
|
static int cpm_init_par_io(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a")
|
|
cpm1_gpiochip_add16(np);
|
|
|
|
for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b")
|
|
cpm1_gpiochip_add32(np);
|
|
|
|
for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c")
|
|
cpm1_gpiochip_add16(np);
|
|
|
|
for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d")
|
|
cpm1_gpiochip_add16(np);
|
|
|
|
/* Port E uses CPM2 layout */
|
|
for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e")
|
|
cpm2_gpiochip_add32(np);
|
|
return 0;
|
|
}
|
|
arch_initcall(cpm_init_par_io);
|
|
|
|
#endif /* CONFIG_8xx_GPIO */
|