![Christophe Leroy](/assets/img/avatar_default.png)
Commit0e6e01ff69
("CPM/QE: use genalloc to manage CPM/QE muram") has changed the way muram is managed. genalloc uses kmalloc(), hence requires the SLAB to be up and running. On powerpc 8xx, cpm_reset() is called early during startup. cpm_reset() then calls cpm_muram_init() before SLAB is available, hence the following Oops. cpm_reset() cannot be called during initcalls because the CPM is needed for console. This patch removes the call to cpm_muram_init() from cpm_reset(). cpm_muram_init() will be called from a new function called cpm_init() which is declared as subsys_initcall, unless cpm_muram_alloc() is called earlier for the serial console in which case cpm_muram_init() will be called from there. The reason for calling it from two places is that some drivers (e.g. i2c-cpm) need some of the initialisations done by cpm_muram_init() but don't call cpm_muram_alloc(). The console driver calls cpm_muram_alloc() but some platforms might not use the CPM serial ports for console. [ 0.000000] Unable to handle kernel paging request for data at address 0x00000008 [ 0.000000] Faulting instruction address: 0xc01acce0 [ 0.000000] Oops: Kernel access of bad area, sig: 11 [#1] [ 0.000000] PREEMPT CMPC885 [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.14-g0886ed8 #5 [ 0.000000] task: c05183e0 ti: c0536000 task.ti: c0536000 [ 0.000000] NIP: c01acce0 LR: c0011068 CTR: 00000000 [ 0.000000] REGS: c0537e50 TRAP: 0300 Not tainted (4.4.14-s3k-dev-g0886ed8-svn) [ 0.000000] MSR: 00001032 <ME,IR,DR,RI> CR: 28044428 XER: 00000000 [ 0.000000] DAR: 00000008 DSISR: c0000000 GPR00: c0011068 c0537f00 c05183e0 00000000 00009000 ffffffff 00000bc0 ffffffff GPR08: ff003000 ff00b000 ff003bbf 00000000 22044422 100d43a8 00000000 07ff94e8 GPR16: 00000000 07bb5d70 00000000 07ff81f4 07ff81f4 07ff81f4 00000000 00000000 GPR24: 07ffb3a0 07fe7628 c0550000 c7ffa190 c0540000 ff003bbf 00000000 00000001 [ 0.000000] NIP [c01acce0] gen_pool_add_virt+0x14/0xdc [ 0.000000] LR [c0011068] cpm_muram_init+0xd4/0x18c [ 0.000000] Call Trace: [ 0.000000] [c0537f00] [00000200] 0x200 (unreliable) [ 0.000000] [c0537f20] [c0011068] cpm_muram_init+0xd4/0x18c [ 0.000000] [c0537f70] [c0494684] cpm_reset+0xb4/0xc8 [ 0.000000] [c0537f90] [c0494c64] cmpc885_setup_arch+0x10/0x30 [ 0.000000] [c0537fa0] [c0493cd4] setup_arch+0x130/0x168 [ 0.000000] [c0537fb0] [c04906bc] start_kernel+0x88/0x380 [ 0.000000] [c0537ff0] [c0002224] start_here+0x38/0x98 [ 0.000000] Instruction dump: [ 0.000000] 91430010 91430014 80010014 83e1000c 7c0803a6 38210010 4e800020 7c0802a6 [ 0.000000] 9421ffe0 bf61000c 90010024 7c7e1b78 <80630008> 7c9c2378 7cc31c30 3863001f [ 0.000000] ---[ end trace dc8fa200cb88537f ]--- fixes:0e6e01ff69
("CPM/QE: use genalloc to manage CPM/QE muram") Cc: stable@vger.linux.org Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> [scottwood: Removed some string changes unrelated to bugfix] Signed-off-by: Scott Wood <oss@buserror.net>
218 lines
5.2 KiB
C
218 lines
5.2 KiB
C
/*
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* Common CPM code
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*
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
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*
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* Some parts derived from commproc.c/cpm2_common.c, which is:
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* Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
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* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
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* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
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* 2006 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/spinlock.h>
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#include <linux/export.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <asm/udbg.h>
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#include <asm/io.h>
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#include <asm/cpm.h>
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#include <asm/fixmap.h>
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#include <soc/fsl/qe/qe.h>
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#include <mm/mmu_decl.h>
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#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
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#include <linux/of_gpio.h>
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#endif
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static int __init cpm_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
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if (!np)
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
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if (!np)
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return -ENODEV;
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cpm_muram_init();
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of_node_put(np);
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return 0;
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}
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subsys_initcall(cpm_init);
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#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
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static u32 __iomem *cpm_udbg_txdesc;
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static u8 __iomem *cpm_udbg_txbuf;
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static void udbg_putc_cpm(char c)
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{
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if (c == '\n')
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udbg_putc_cpm('\r');
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while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
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;
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out_8(cpm_udbg_txbuf, c);
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out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
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}
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void __init udbg_init_cpm(void)
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{
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#ifdef CONFIG_PPC_8xx
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cpm_udbg_txdesc = (u32 __iomem __force *)
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(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +
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VIRT_IMMR_BASE);
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cpm_udbg_txbuf = (u8 __iomem __force *)
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(in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +
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VIRT_IMMR_BASE);
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#else
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cpm_udbg_txdesc = (u32 __iomem __force *)
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CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
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cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
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#endif
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if (cpm_udbg_txdesc) {
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#ifdef CONFIG_CPM2
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setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
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#endif
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udbg_putc = udbg_putc_cpm;
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}
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}
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#endif
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#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
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struct cpm2_ioports {
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u32 dir, par, sor, odr, dat;
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u32 res[3];
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};
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struct cpm2_gpio32_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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/* shadowed data register to clear/set bits safely */
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u32 cpdata;
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};
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static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
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{
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struct cpm2_gpio32_chip *cpm2_gc =
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container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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cpm2_gc->cpdata = in_be32(&iop->dat);
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}
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static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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u32 pin_mask;
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pin_mask = 1 << (31 - gpio);
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return !!(in_be32(&iop->dat) & pin_mask);
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}
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static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
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int value)
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{
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struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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if (value)
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cpm2_gc->cpdata |= pin_mask;
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else
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cpm2_gc->cpdata &= ~pin_mask;
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out_be32(&iop->dat, cpm2_gc->cpdata);
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}
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static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
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unsigned long flags;
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u32 pin_mask = 1 << (31 - gpio);
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spin_lock_irqsave(&cpm2_gc->lock, flags);
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__cpm2_gpio32_set(mm_gc, pin_mask, value);
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spin_unlock_irqrestore(&cpm2_gc->lock, flags);
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}
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static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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unsigned long flags;
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u32 pin_mask = 1 << (31 - gpio);
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spin_lock_irqsave(&cpm2_gc->lock, flags);
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setbits32(&iop->dir, pin_mask);
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__cpm2_gpio32_set(mm_gc, pin_mask, val);
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spin_unlock_irqrestore(&cpm2_gc->lock, flags);
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return 0;
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}
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static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
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struct cpm2_ioports __iomem *iop = mm_gc->regs;
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unsigned long flags;
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u32 pin_mask = 1 << (31 - gpio);
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spin_lock_irqsave(&cpm2_gc->lock, flags);
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clrbits32(&iop->dir, pin_mask);
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spin_unlock_irqrestore(&cpm2_gc->lock, flags);
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return 0;
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}
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int cpm2_gpiochip_add32(struct device_node *np)
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{
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struct cpm2_gpio32_chip *cpm2_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct gpio_chip *gc;
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cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
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if (!cpm2_gc)
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return -ENOMEM;
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spin_lock_init(&cpm2_gc->lock);
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mm_gc = &cpm2_gc->mm_gc;
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gc = &mm_gc->gc;
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mm_gc->save_regs = cpm2_gpio32_save_regs;
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gc->ngpio = 32;
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gc->direction_input = cpm2_gpio32_dir_in;
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gc->direction_output = cpm2_gpio32_dir_out;
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gc->get = cpm2_gpio32_get;
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gc->set = cpm2_gpio32_set;
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return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
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}
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#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
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