![Eugeniy Paltsev](/assets/img/avatar_default.png)
As of today we use hardcoded MCIP debug mask, so if we launch kernel via debugger and kick fever cores than HW has all cpus hang at the momemt of setup MCIP debug mask. So update MCIP debug mask when the new cpu came online, instead of use hardcoded MCIP debug mask. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
377 lines
9.3 KiB
C
377 lines
9.3 KiB
C
/*
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* ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
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*
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* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/smp.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/spinlock.h>
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#include <soc/arc/mcip.h>
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#include <asm/irqflags-arcv2.h>
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#include <asm/setup.h>
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static DEFINE_RAW_SPINLOCK(mcip_lock);
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#ifdef CONFIG_SMP
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static char smp_cpuinfo_buf[128];
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/*
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* Set mask to halt GFRC if any online core in SMP cluster is halted.
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* Only works for ARC HS v3.0+, on earlier versions has no effect.
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*/
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static void mcip_update_gfrc_halt_mask(int cpu)
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{
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struct bcr_generic gfrc;
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unsigned long flags;
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u32 gfrc_halt_mask;
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READ_BCR(ARC_REG_GFRC_BUILD, gfrc);
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/*
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* CMD_GFRC_SET_CORE and CMD_GFRC_READ_CORE commands were added in
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* GFRC 0x3 version.
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*/
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if (gfrc.ver < 0x3)
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return;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd(CMD_GFRC_READ_CORE, 0);
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gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
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gfrc_halt_mask |= BIT(cpu);
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__mcip_cmd_data(CMD_GFRC_SET_CORE, 0, gfrc_halt_mask);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void mcip_update_debug_halt_mask(int cpu)
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{
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u32 mcip_mask = 0;
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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/*
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* mcip_mask is same for CMD_DEBUG_SET_SELECT and CMD_DEBUG_SET_MASK
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* commands. So read it once instead of reading both CMD_DEBUG_READ_MASK
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* and CMD_DEBUG_READ_SELECT.
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*/
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__mcip_cmd(CMD_DEBUG_READ_SELECT, 0);
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mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
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mcip_mask |= BIT(cpu);
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__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, mcip_mask);
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/*
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* Parameter specified halt cause:
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* STATUS32[H]/actionpoint/breakpoint/self-halt
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* We choose all of them (0xF).
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*/
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__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xF, mcip_mask);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void mcip_setup_per_cpu(int cpu)
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{
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struct mcip_bcr mp;
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READ_BCR(ARC_REG_MCIP_BCR, mp);
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smp_ipi_irq_setup(cpu, IPI_IRQ);
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smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);
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/* Update GFRC halt mask as new CPU came online */
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if (mp.gfrc)
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mcip_update_gfrc_halt_mask(cpu);
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/* Update MCIP debug mask as new CPU came online */
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if (mp.dbg)
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mcip_update_debug_halt_mask(cpu);
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}
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static void mcip_ipi_send(int cpu)
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{
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unsigned long flags;
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int ipi_was_pending;
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/* ARConnect can only send IPI to others */
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if (unlikely(cpu == raw_smp_processor_id())) {
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arc_softirq_trigger(SOFTIRQ_IRQ);
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return;
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}
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raw_spin_lock_irqsave(&mcip_lock, flags);
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/*
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* If receiver already has a pending interrupt, elide sending this one.
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* Linux cross core calling works well with concurrent IPIs
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* coalesced into one
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* see arch/arc/kernel/smp.c: ipi_send_msg_one()
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*/
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__mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
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ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
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if (!ipi_was_pending)
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__mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void mcip_ipi_clear(int irq)
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{
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unsigned int cpu, c;
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unsigned long flags;
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if (unlikely(irq == SOFTIRQ_IRQ)) {
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arc_softirq_clear(irq);
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return;
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}
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raw_spin_lock_irqsave(&mcip_lock, flags);
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/* Who sent the IPI */
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__mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
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cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
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/*
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* In rare case, multiple concurrent IPIs sent to same target can
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* possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
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* "vectored" (multiple bits sets) as opposed to typical single bit
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*/
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do {
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c = __ffs(cpu); /* 0,1,2,3 */
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__mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
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cpu &= ~(1U << c);
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} while (cpu);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void mcip_probe_n_setup(void)
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{
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struct mcip_bcr mp;
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READ_BCR(ARC_REG_MCIP_BCR, mp);
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sprintf(smp_cpuinfo_buf,
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"Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
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mp.ver, mp.num_cores,
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IS_AVAIL1(mp.ipi, "IPI "),
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IS_AVAIL1(mp.idu, "IDU "),
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IS_AVAIL1(mp.dbg, "DEBUG "),
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IS_AVAIL1(mp.gfrc, "GFRC"));
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cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
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}
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struct plat_smp_ops plat_smp_ops = {
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.info = smp_cpuinfo_buf,
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.init_early_smp = mcip_probe_n_setup,
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.init_per_cpu = mcip_setup_per_cpu,
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.ipi_send = mcip_ipi_send,
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.ipi_clear = mcip_ipi_clear,
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};
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#endif
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/***************************************************************************
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* ARCv2 Interrupt Distribution Unit (IDU)
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*
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* Connects external "COMMON" IRQs to core intc, providing:
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* -dynamic routing (IRQ affinity)
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* -load balancing (Round Robin interrupt distribution)
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* -1:N distribution
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*
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* It physically resides in the MCIP hw block
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*/
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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/*
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* Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
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*/
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static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
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{
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__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
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}
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static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
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unsigned int distr)
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{
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union {
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unsigned int word;
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struct {
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unsigned int distr:2, pad:2, lvl:1, pad2:27;
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};
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} data;
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data.distr = distr;
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data.lvl = lvl;
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__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
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}
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static void idu_irq_mask_raw(irq_hw_number_t hwirq)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static void idu_irq_mask(struct irq_data *data)
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{
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idu_irq_mask_raw(data->hwirq);
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}
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static void idu_irq_unmask(struct irq_data *data)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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__mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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}
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static int
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idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
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bool force)
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{
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unsigned long flags;
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cpumask_t online;
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unsigned int destination_bits;
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unsigned int distribution_mode;
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/* errout if no online cpu per @cpumask */
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if (!cpumask_and(&online, cpumask, cpu_online_mask))
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return -EINVAL;
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raw_spin_lock_irqsave(&mcip_lock, flags);
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destination_bits = cpumask_bits(&online)[0];
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idu_set_dest(data->hwirq, destination_bits);
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if (ffs(destination_bits) == fls(destination_bits))
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distribution_mode = IDU_M_DISTRI_DEST;
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else
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distribution_mode = IDU_M_DISTRI_RR;
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idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode);
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raw_spin_unlock_irqrestore(&mcip_lock, flags);
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return IRQ_SET_MASK_OK;
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}
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static void idu_irq_enable(struct irq_data *data)
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{
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/*
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* By default send all common interrupts to all available online CPUs.
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* The affinity of common interrupts in IDU must be set manually since
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* in some cases the kernel will not call irq_set_affinity() by itself:
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* 1. When the kernel is not configured with support of SMP.
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* 2. When the kernel is configured with support of SMP but upper
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* interrupt controllers does not support setting of the affinity
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* and cannot propagate it to IDU.
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*/
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idu_irq_set_affinity(data, cpu_online_mask, false);
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idu_irq_unmask(data);
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}
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static struct irq_chip idu_irq_chip = {
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.name = "MCIP IDU Intc",
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.irq_mask = idu_irq_mask,
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.irq_unmask = idu_irq_unmask,
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.irq_enable = idu_irq_enable,
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#ifdef CONFIG_SMP
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.irq_set_affinity = idu_irq_set_affinity,
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#endif
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};
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static void idu_cascade_isr(struct irq_desc *desc)
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{
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struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
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struct irq_chip *core_chip = irq_desc_get_chip(desc);
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irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
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irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
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chained_irq_enter(core_chip, desc);
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generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
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chained_irq_exit(core_chip, desc);
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}
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static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
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irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
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return 0;
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}
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static const struct irq_domain_ops idu_irq_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = idu_irq_map,
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};
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/*
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* [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
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* [24, 23+C]: If C > 0 then "C" common IRQs
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* [24+C, N]: Not statically assigned, private-per-core
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*/
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static int __init
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idu_of_init(struct device_node *intc, struct device_node *parent)
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{
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struct irq_domain *domain;
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int nr_irqs;
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int i, virq;
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struct mcip_bcr mp;
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struct mcip_idu_bcr idu_bcr;
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READ_BCR(ARC_REG_MCIP_BCR, mp);
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if (!mp.idu)
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panic("IDU not detected, but DeviceTree using it");
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READ_BCR(ARC_REG_MCIP_IDU_BCR, idu_bcr);
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nr_irqs = mcip_idu_bcr_to_nr_irqs(idu_bcr);
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pr_info("MCIP: IDU supports %u common irqs\n", nr_irqs);
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domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
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/* Parent interrupts (core-intc) are already mapped */
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for (i = 0; i < nr_irqs; i++) {
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/* Mask all common interrupts by default */
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idu_irq_mask_raw(i);
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/*
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* Return parent uplink IRQs (towards core intc) 24,25,.....
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* this step has been done before already
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* however we need it to get the parent virq and set IDU handler
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* as first level isr
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*/
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virq = irq_create_mapping(NULL, i + FIRST_EXT_IRQ);
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BUG_ON(!virq);
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irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain);
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}
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__mcip_cmd(CMD_IDU_ENABLE, 0);
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return 0;
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}
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IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);
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