![Vineet Gupta](/assets/img/avatar_default.png)
use ffz primitive which maps to ARCv2 instruction, vs. non atomic __test_and_set_bit It is unlikely if we will even have more than 32 counters, but still add a BUILD_BUG to catch that Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
563 lines
14 KiB
C
563 lines
14 KiB
C
/*
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* Linux performance counter support for ARC700 series
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*
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* Copyright (C) 2013-2015 Synopsys, Inc. (www.synopsys.com)
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*
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* This code is inspired by the perf support of various other architectures.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <asm/arcregs.h>
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#include <asm/stacktrace.h>
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struct arc_pmu {
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struct pmu pmu;
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unsigned int irq;
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int n_counters;
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u64 max_period;
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int ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
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};
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struct arc_pmu_cpu {
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/*
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* A 1 bit for an index indicates that the counter is being used for
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* an event. A 0 means that the counter can be used.
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*/
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unsigned long used_mask[BITS_TO_LONGS(ARC_PERF_MAX_COUNTERS)];
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/*
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* The events that are active on the PMU for the given index.
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*/
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struct perf_event *act_counter[ARC_PERF_MAX_COUNTERS];
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};
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struct arc_callchain_trace {
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int depth;
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void *perf_stuff;
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};
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static int callchain_trace(unsigned int addr, void *data)
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{
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struct arc_callchain_trace *ctrl = data;
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struct perf_callchain_entry_ctx *entry = ctrl->perf_stuff;
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perf_callchain_store(entry, addr);
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if (ctrl->depth++ < 3)
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return 0;
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return -1;
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}
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void
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perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
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{
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struct arc_callchain_trace ctrl = {
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.depth = 0,
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.perf_stuff = entry,
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};
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arc_unwind_core(NULL, regs, callchain_trace, &ctrl);
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}
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void
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perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
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{
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/*
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* User stack can't be unwound trivially with kernel dwarf unwinder
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* So for now just record the user PC
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*/
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perf_callchain_store(entry, instruction_pointer(regs));
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}
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static struct arc_pmu *arc_pmu;
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static DEFINE_PER_CPU(struct arc_pmu_cpu, arc_pmu_cpu);
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/* read counter #idx; note that counter# != event# on ARC! */
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static uint64_t arc_pmu_read_counter(int idx)
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{
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uint32_t tmp;
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uint64_t result;
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/*
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* ARC supports making 'snapshots' of the counters, so we don't
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* need to care about counters wrapping to 0 underneath our feet
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*/
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
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result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
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result |= read_aux_reg(ARC_REG_PCT_SNAPL);
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return result;
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}
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static void arc_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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uint64_t prev_raw_count = local64_read(&hwc->prev_count);
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uint64_t new_raw_count = arc_pmu_read_counter(idx);
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int64_t delta = new_raw_count - prev_raw_count;
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/*
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* We aren't afraid of hwc->prev_count changing beneath our feet
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* because there's no way for us to re-enter this function anytime.
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*/
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local64_set(&hwc->prev_count, new_raw_count);
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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}
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static void arc_pmu_read(struct perf_event *event)
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{
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arc_perf_event_update(event, &event->hw, event->hw.idx);
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}
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static int arc_pmu_cache_event(u64 config)
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{
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unsigned int cache_type, cache_op, cache_result;
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int ret;
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cache_type = (config >> 0) & 0xff;
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cache_op = (config >> 8) & 0xff;
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cache_result = (config >> 16) & 0xff;
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if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
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return -EINVAL;
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if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
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return -EINVAL;
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if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
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return -EINVAL;
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ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];
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if (ret == CACHE_OP_UNSUPPORTED)
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return -ENOENT;
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pr_debug("init cache event: type/op/result %d/%d/%d with h/w %d \'%s\'\n",
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cache_type, cache_op, cache_result, ret,
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arc_pmu_ev_hw_map[ret]);
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return ret;
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}
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/* initializes hw_perf_event structure if event is supported */
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static int arc_pmu_event_init(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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int ret;
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if (!is_sampling_event(event)) {
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hwc->sample_period = arc_pmu->max_period;
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hwc->last_period = hwc->sample_period;
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local64_set(&hwc->period_left, hwc->sample_period);
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}
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hwc->config = 0;
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if (is_isa_arcv2()) {
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/* "exclude user" means "count only kernel" */
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if (event->attr.exclude_user)
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hwc->config |= ARC_REG_PCT_CONFIG_KERN;
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/* "exclude kernel" means "count only user" */
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if (event->attr.exclude_kernel)
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hwc->config |= ARC_REG_PCT_CONFIG_USER;
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}
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switch (event->attr.type) {
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case PERF_TYPE_HARDWARE:
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if (event->attr.config >= PERF_COUNT_HW_MAX)
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return -ENOENT;
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if (arc_pmu->ev_hw_idx[event->attr.config] < 0)
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return -ENOENT;
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hwc->config |= arc_pmu->ev_hw_idx[event->attr.config];
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pr_debug("init event %d with h/w %08x \'%s\'\n",
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(int)event->attr.config, (int)hwc->config,
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arc_pmu_ev_hw_map[event->attr.config]);
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return 0;
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case PERF_TYPE_HW_CACHE:
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ret = arc_pmu_cache_event(event->attr.config);
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if (ret < 0)
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return ret;
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hwc->config |= arc_pmu->ev_hw_idx[ret];
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pr_debug("init cache event with h/w %08x \'%s\'\n",
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(int)hwc->config, arc_pmu_ev_hw_map[ret]);
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return 0;
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default:
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return -ENOENT;
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}
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}
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/* starts all counters */
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static void arc_pmu_enable(struct pmu *pmu)
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{
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uint32_t tmp;
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
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}
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/* stops all counters */
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static void arc_pmu_disable(struct pmu *pmu)
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{
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uint32_t tmp;
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tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
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write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
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}
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static int arc_pmu_event_set_period(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int idx = hwc->idx;
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int overflow = 0;
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u64 value;
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if (unlikely(left <= -period)) {
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/* left underflowed by more than period. */
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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} else if (unlikely(left <= 0)) {
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/* left underflowed by less than period. */
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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overflow = 1;
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}
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if (left > arc_pmu->max_period)
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left = arc_pmu->max_period;
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value = arc_pmu->max_period - left;
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local64_set(&hwc->prev_count, value);
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/* Select counter */
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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/* Write value */
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write_aux_reg(ARC_REG_PCT_COUNTL, (u32)value);
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write_aux_reg(ARC_REG_PCT_COUNTH, (value >> 32));
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perf_event_update_userpage(event);
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return overflow;
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}
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/*
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* Assigns hardware counter to hardware condition.
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* Note that there is no separate start/stop mechanism;
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* stopping is achieved by assigning the 'never' condition
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*/
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static void arc_pmu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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if (WARN_ON_ONCE(idx == -1))
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return;
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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arc_pmu_event_set_period(event);
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/* Enable interrupt for this counter */
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if (is_sampling_event(event))
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write_aux_reg(ARC_REG_PCT_INT_CTRL,
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read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
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/* enable ARC pmu here */
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write_aux_reg(ARC_REG_PCT_INDEX, idx); /* counter # */
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write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config); /* condition */
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}
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static void arc_pmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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/* Disable interrupt for this counter */
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if (is_sampling_event(event)) {
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/*
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* Reset interrupt flag by writing of 1. This is required
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* to make sure pending interrupt was not left.
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*/
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write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);
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write_aux_reg(ARC_REG_PCT_INT_CTRL,
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read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~(1 << idx));
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}
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if (!(event->hw.state & PERF_HES_STOPPED)) {
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/* stop ARC pmu here */
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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/* condition code #0 is always "never" */
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write_aux_reg(ARC_REG_PCT_CONFIG, 0);
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event->hw.state |= PERF_HES_STOPPED;
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}
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if ((flags & PERF_EF_UPDATE) &&
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!(event->hw.state & PERF_HES_UPTODATE)) {
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arc_perf_event_update(event, &event->hw, idx);
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event->hw.state |= PERF_HES_UPTODATE;
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}
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}
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static void arc_pmu_del(struct perf_event *event, int flags)
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{
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struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
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arc_pmu_stop(event, PERF_EF_UPDATE);
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__clear_bit(event->hw.idx, pmu_cpu->used_mask);
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pmu_cpu->act_counter[event->hw.idx] = 0;
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perf_event_update_userpage(event);
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}
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/* allocate hardware counter and optionally start counting */
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static int arc_pmu_add(struct perf_event *event, int flags)
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{
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struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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idx = ffz(pmu_cpu->used_mask[0]);
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if (idx == arc_pmu->n_counters)
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return -EAGAIN;
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__set_bit(idx, pmu_cpu->used_mask);
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hwc->idx = idx;
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write_aux_reg(ARC_REG_PCT_INDEX, idx);
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pmu_cpu->act_counter[idx] = event;
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if (is_sampling_event(event)) {
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/* Mimic full counter overflow as other arches do */
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write_aux_reg(ARC_REG_PCT_INT_CNTL, (u32)arc_pmu->max_period);
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write_aux_reg(ARC_REG_PCT_INT_CNTH,
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(arc_pmu->max_period >> 32));
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}
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write_aux_reg(ARC_REG_PCT_CONFIG, 0);
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write_aux_reg(ARC_REG_PCT_COUNTL, 0);
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write_aux_reg(ARC_REG_PCT_COUNTH, 0);
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local64_set(&hwc->prev_count, 0);
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hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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if (flags & PERF_EF_START)
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arc_pmu_start(event, PERF_EF_RELOAD);
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perf_event_update_userpage(event);
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return 0;
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}
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#ifdef CONFIG_ISA_ARCV2
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static irqreturn_t arc_pmu_intr(int irq, void *dev)
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{
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struct perf_sample_data data;
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struct arc_pmu_cpu *pmu_cpu = this_cpu_ptr(&arc_pmu_cpu);
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struct pt_regs *regs;
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unsigned int active_ints;
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int idx;
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arc_pmu_disable(&arc_pmu->pmu);
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active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT);
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if (!active_ints)
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goto done;
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regs = get_irq_regs();
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do {
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struct perf_event *event;
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struct hw_perf_event *hwc;
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idx = __ffs(active_ints);
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/* Reset interrupt flag by writing of 1 */
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write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);
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/*
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* On reset of "interrupt active" bit corresponding
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* "interrupt enable" bit gets automatically reset as well.
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* Now we need to re-enable interrupt for the counter.
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*/
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write_aux_reg(ARC_REG_PCT_INT_CTRL,
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read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx));
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event = pmu_cpu->act_counter[idx];
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hwc = &event->hw;
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WARN_ON_ONCE(hwc->idx != idx);
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arc_perf_event_update(event, &event->hw, event->hw.idx);
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perf_sample_data_init(&data, 0, hwc->last_period);
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if (arc_pmu_event_set_period(event)) {
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if (perf_event_overflow(event, &data, regs))
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arc_pmu_stop(event, 0);
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}
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active_ints &= ~(1U << idx);
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} while (active_ints);
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done:
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arc_pmu_enable(&arc_pmu->pmu);
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return IRQ_HANDLED;
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}
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#else
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static irqreturn_t arc_pmu_intr(int irq, void *dev)
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{
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return IRQ_NONE;
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}
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#endif /* CONFIG_ISA_ARCV2 */
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static void arc_cpu_pmu_irq_init(void *data)
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{
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int irq = *(int *)data;
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enable_percpu_irq(irq, IRQ_TYPE_NONE);
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/* Clear all pending interrupt flags */
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write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);
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}
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static int arc_pmu_device_probe(struct platform_device *pdev)
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{
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struct arc_reg_pct_build pct_bcr;
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struct arc_reg_cc_build cc_bcr;
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int i, j, has_interrupts;
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int counter_size; /* in bits */
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union cc_name {
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struct {
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uint32_t word0, word1;
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char sentinel;
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} indiv;
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char str[9];
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} cc_name;
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READ_BCR(ARC_REG_PCT_BUILD, pct_bcr);
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if (!pct_bcr.v) {
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pr_err("This core does not have performance counters!\n");
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return -ENODEV;
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}
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BUILD_BUG_ON(ARC_PERF_MAX_COUNTERS > 32);
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BUG_ON(pct_bcr.c > ARC_PERF_MAX_COUNTERS);
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READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
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BUG_ON(!cc_bcr.v); /* Counters exist but No countable conditions ? */
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arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu), GFP_KERNEL);
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if (!arc_pmu)
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return -ENOMEM;
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has_interrupts = is_isa_arcv2() ? pct_bcr.i : 0;
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arc_pmu->n_counters = pct_bcr.c;
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counter_size = 32 + (pct_bcr.s << 4);
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arc_pmu->max_period = (1ULL << counter_size) / 2 - 1ULL;
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pr_info("ARC perf\t: %d counters (%d bits), %d conditions%s\n",
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arc_pmu->n_counters, counter_size, cc_bcr.c,
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has_interrupts ? ", [overflow IRQ support]":"");
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cc_name.str[8] = 0;
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for (i = 0; i < PERF_COUNT_ARC_HW_MAX; i++)
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arc_pmu->ev_hw_idx[i] = -1;
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/* loop thru all available h/w condition indexes */
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for (j = 0; j < cc_bcr.c; j++) {
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write_aux_reg(ARC_REG_CC_INDEX, j);
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cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
|
|
cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
|
|
|
|
/* See if it has been mapped to a perf event_id */
|
|
for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
|
|
if (arc_pmu_ev_hw_map[i] &&
|
|
!strcmp(arc_pmu_ev_hw_map[i], cc_name.str) &&
|
|
strlen(arc_pmu_ev_hw_map[i])) {
|
|
pr_debug("mapping perf event %2d to h/w event \'%8s\' (idx %d)\n",
|
|
i, cc_name.str, j);
|
|
arc_pmu->ev_hw_idx[i] = j;
|
|
}
|
|
}
|
|
}
|
|
|
|
arc_pmu->pmu = (struct pmu) {
|
|
.pmu_enable = arc_pmu_enable,
|
|
.pmu_disable = arc_pmu_disable,
|
|
.event_init = arc_pmu_event_init,
|
|
.add = arc_pmu_add,
|
|
.del = arc_pmu_del,
|
|
.start = arc_pmu_start,
|
|
.stop = arc_pmu_stop,
|
|
.read = arc_pmu_read,
|
|
};
|
|
|
|
if (has_interrupts) {
|
|
int irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
pr_err("Cannot get IRQ number for the platform\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
arc_pmu->irq = irq;
|
|
|
|
/* intc map function ensures irq_set_percpu_devid() called */
|
|
request_percpu_irq(irq, arc_pmu_intr, "ARC perf counters",
|
|
this_cpu_ptr(&arc_pmu_cpu));
|
|
|
|
on_each_cpu(arc_cpu_pmu_irq_init, &irq, 1);
|
|
|
|
} else
|
|
arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
|
|
|
|
return perf_pmu_register(&arc_pmu->pmu, pdev->name, PERF_TYPE_RAW);
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id arc_pmu_match[] = {
|
|
{ .compatible = "snps,arc700-pct" },
|
|
{ .compatible = "snps,archs-pct" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, arc_pmu_match);
|
|
#endif
|
|
|
|
static struct platform_driver arc_pmu_driver = {
|
|
.driver = {
|
|
.name = "arc-pct",
|
|
.of_match_table = of_match_ptr(arc_pmu_match),
|
|
},
|
|
.probe = arc_pmu_device_probe,
|
|
};
|
|
|
|
module_platform_driver(arc_pmu_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>");
|
|
MODULE_DESCRIPTION("ARC PMU driver");
|