![Michel Dänzer](/assets/img/avatar_default.png)
Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
637 lines
16 KiB
C
637 lines
16 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <linux/list.h>
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#include <drm/drmP.h>
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#include "radeon_drm.h"
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#include "radeon.h"
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struct radeon_object {
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struct ttm_buffer_object tobj;
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struct list_head list;
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struct radeon_device *rdev;
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struct drm_gem_object *gobj;
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struct ttm_bo_kmap_obj kmap;
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unsigned pin_count;
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uint64_t gpu_addr;
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void *kptr;
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bool is_iomem;
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uint32_t tiling_flags;
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uint32_t pitch;
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int surface_reg;
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};
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int radeon_ttm_init(struct radeon_device *rdev);
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void radeon_ttm_fini(struct radeon_device *rdev);
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/*
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* To exclude mutual BO access we rely on bo_reserve exclusion, as all
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* function are calling it.
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*/
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static int radeon_object_reserve(struct radeon_object *robj, bool interruptible)
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{
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return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0);
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}
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static void radeon_object_unreserve(struct radeon_object *robj)
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{
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ttm_bo_unreserve(&robj->tobj);
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}
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static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj)
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{
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struct radeon_object *robj;
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robj = container_of(tobj, struct radeon_object, tobj);
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list_del_init(&robj->list);
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radeon_object_clear_surface_reg(robj);
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kfree(robj);
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}
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static inline void radeon_object_gpu_addr(struct radeon_object *robj)
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{
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/* Default gpu address */
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robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
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if (robj->tobj.mem.mm_node == NULL) {
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return;
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}
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robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT;
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switch (robj->tobj.mem.mem_type) {
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case TTM_PL_VRAM:
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robj->gpu_addr += (u64)robj->rdev->mc.vram_location;
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break;
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case TTM_PL_TT:
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robj->gpu_addr += (u64)robj->rdev->mc.gtt_location;
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break;
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default:
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DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type);
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robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
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return;
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}
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}
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static inline uint32_t radeon_object_flags_from_domain(uint32_t domain)
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{
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uint32_t flags = 0;
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if (domain & RADEON_GEM_DOMAIN_VRAM) {
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flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
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}
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if (domain & RADEON_GEM_DOMAIN_GTT) {
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flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
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}
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if (domain & RADEON_GEM_DOMAIN_CPU) {
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flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
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}
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if (!flags) {
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flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
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}
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return flags;
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}
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int radeon_object_create(struct radeon_device *rdev,
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struct drm_gem_object *gobj,
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unsigned long size,
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bool kernel,
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uint32_t domain,
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bool interruptible,
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struct radeon_object **robj_ptr)
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{
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struct radeon_object *robj;
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enum ttm_bo_type type;
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uint32_t flags;
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int r;
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if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
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rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
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}
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if (kernel) {
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type = ttm_bo_type_kernel;
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} else {
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type = ttm_bo_type_device;
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}
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*robj_ptr = NULL;
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robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL);
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if (robj == NULL) {
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return -ENOMEM;
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}
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robj->rdev = rdev;
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robj->gobj = gobj;
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robj->surface_reg = -1;
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INIT_LIST_HEAD(&robj->list);
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flags = radeon_object_flags_from_domain(domain);
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r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags,
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0, 0, false, NULL, size,
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&radeon_ttm_object_object_destroy);
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if (unlikely(r != 0)) {
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/* ttm call radeon_ttm_object_object_destroy if error happen */
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DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n",
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size, flags, 0);
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return r;
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}
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*robj_ptr = robj;
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if (gobj) {
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list_add_tail(&robj->list, &rdev->gem.objects);
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}
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return 0;
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}
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int radeon_object_kmap(struct radeon_object *robj, void **ptr)
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{
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int r;
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spin_lock(&robj->tobj.lock);
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if (robj->kptr) {
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if (ptr) {
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*ptr = robj->kptr;
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}
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spin_unlock(&robj->tobj.lock);
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return 0;
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}
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spin_unlock(&robj->tobj.lock);
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r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap);
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if (r) {
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return r;
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}
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spin_lock(&robj->tobj.lock);
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robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem);
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spin_unlock(&robj->tobj.lock);
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if (ptr) {
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*ptr = robj->kptr;
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}
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radeon_object_check_tiling(robj, 0, 0);
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return 0;
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}
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void radeon_object_kunmap(struct radeon_object *robj)
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{
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spin_lock(&robj->tobj.lock);
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if (robj->kptr == NULL) {
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spin_unlock(&robj->tobj.lock);
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return;
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}
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robj->kptr = NULL;
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spin_unlock(&robj->tobj.lock);
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radeon_object_check_tiling(robj, 0, 0);
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ttm_bo_kunmap(&robj->kmap);
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}
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void radeon_object_unref(struct radeon_object **robj)
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{
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struct ttm_buffer_object *tobj;
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if ((*robj) == NULL) {
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return;
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}
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tobj = &((*robj)->tobj);
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ttm_bo_unref(&tobj);
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if (tobj == NULL) {
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*robj = NULL;
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}
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}
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int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset)
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{
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*offset = robj->tobj.addr_space_offset;
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return 0;
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}
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int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
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uint64_t *gpu_addr)
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{
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uint32_t flags;
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uint32_t tmp;
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int r;
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flags = radeon_object_flags_from_domain(domain);
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spin_lock(&robj->tobj.lock);
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if (robj->pin_count) {
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robj->pin_count++;
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if (gpu_addr != NULL) {
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*gpu_addr = robj->gpu_addr;
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}
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spin_unlock(&robj->tobj.lock);
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return 0;
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}
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spin_unlock(&robj->tobj.lock);
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r = radeon_object_reserve(robj, false);
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to reserve object for pinning it.\n");
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return r;
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}
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tmp = robj->tobj.mem.placement;
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ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
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robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING;
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r = ttm_buffer_object_validate(&robj->tobj,
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robj->tobj.proposed_placement,
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false, false);
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radeon_object_gpu_addr(robj);
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if (gpu_addr != NULL) {
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*gpu_addr = robj->gpu_addr;
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}
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robj->pin_count = 1;
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to pin object.\n");
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}
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radeon_object_unreserve(robj);
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return r;
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}
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void radeon_object_unpin(struct radeon_object *robj)
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{
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uint32_t flags;
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int r;
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spin_lock(&robj->tobj.lock);
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if (!robj->pin_count) {
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spin_unlock(&robj->tobj.lock);
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printk(KERN_WARNING "Unpin not necessary for %p !\n", robj);
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return;
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}
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robj->pin_count--;
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if (robj->pin_count) {
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spin_unlock(&robj->tobj.lock);
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return;
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}
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spin_unlock(&robj->tobj.lock);
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r = radeon_object_reserve(robj, false);
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to reserve object for unpinning it.\n");
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return;
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}
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flags = robj->tobj.mem.placement;
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robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT;
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r = ttm_buffer_object_validate(&robj->tobj,
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robj->tobj.proposed_placement,
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false, false);
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to unpin buffer.\n");
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}
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radeon_object_unreserve(robj);
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}
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int radeon_object_wait(struct radeon_object *robj)
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{
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int r = 0;
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/* FIXME: should use block reservation instead */
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r = radeon_object_reserve(robj, true);
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to reserve object for waiting.\n");
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return r;
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}
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spin_lock(&robj->tobj.lock);
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if (robj->tobj.sync_obj) {
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r = ttm_bo_wait(&robj->tobj, true, true, false);
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}
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spin_unlock(&robj->tobj.lock);
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radeon_object_unreserve(robj);
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return r;
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}
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int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement)
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{
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int r = 0;
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r = radeon_object_reserve(robj, true);
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to reserve object for waiting.\n");
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return r;
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}
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spin_lock(&robj->tobj.lock);
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*cur_placement = robj->tobj.mem.mem_type;
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if (robj->tobj.sync_obj) {
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r = ttm_bo_wait(&robj->tobj, true, true, true);
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}
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spin_unlock(&robj->tobj.lock);
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radeon_object_unreserve(robj);
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return r;
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}
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int radeon_object_evict_vram(struct radeon_device *rdev)
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{
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if (rdev->flags & RADEON_IS_IGP) {
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/* Useless to evict on IGP chips */
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return 0;
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}
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return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
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}
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void radeon_object_force_delete(struct radeon_device *rdev)
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{
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struct radeon_object *robj, *n;
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struct drm_gem_object *gobj;
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if (list_empty(&rdev->gem.objects)) {
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return;
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}
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DRM_ERROR("Userspace still has active objects !\n");
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list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) {
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mutex_lock(&rdev->ddev->struct_mutex);
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gobj = robj->gobj;
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DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n",
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gobj, robj, (unsigned long)gobj->size,
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*((unsigned long *)&gobj->refcount));
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list_del_init(&robj->list);
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radeon_object_unref(&robj);
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gobj->driver_private = NULL;
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drm_gem_object_unreference(gobj);
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mutex_unlock(&rdev->ddev->struct_mutex);
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}
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}
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int radeon_object_init(struct radeon_device *rdev)
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{
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/* Add an MTRR for the VRAM */
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rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
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MTRR_TYPE_WRCOMB, 1);
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DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
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rdev->mc.mc_vram_size >> 20,
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(unsigned long long)rdev->mc.aper_size >> 20);
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DRM_INFO("RAM width %dbits %cDR\n",
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rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
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return radeon_ttm_init(rdev);
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}
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void radeon_object_fini(struct radeon_device *rdev)
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{
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radeon_ttm_fini(rdev);
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}
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void radeon_object_list_add_object(struct radeon_object_list *lobj,
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struct list_head *head)
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{
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if (lobj->wdomain) {
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list_add(&lobj->list, head);
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} else {
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list_add_tail(&lobj->list, head);
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}
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}
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int radeon_object_list_reserve(struct list_head *head)
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{
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struct radeon_object_list *lobj;
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struct list_head *i;
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int r;
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list_for_each(i, head) {
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lobj = list_entry(i, struct radeon_object_list, list);
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if (!lobj->robj->pin_count) {
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r = radeon_object_reserve(lobj->robj, true);
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to reserve object.\n");
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return r;
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}
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} else {
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}
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}
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return 0;
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}
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void radeon_object_list_unreserve(struct list_head *head)
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{
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struct radeon_object_list *lobj;
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struct list_head *i;
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list_for_each(i, head) {
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lobj = list_entry(i, struct radeon_object_list, list);
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if (!lobj->robj->pin_count) {
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radeon_object_unreserve(lobj->robj);
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} else {
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}
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}
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}
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int radeon_object_list_validate(struct list_head *head, void *fence)
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{
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struct radeon_object_list *lobj;
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struct radeon_object *robj;
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struct radeon_fence *old_fence = NULL;
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struct list_head *i;
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int r;
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r = radeon_object_list_reserve(head);
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if (unlikely(r != 0)) {
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radeon_object_list_unreserve(head);
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return r;
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}
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list_for_each(i, head) {
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lobj = list_entry(i, struct radeon_object_list, list);
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robj = lobj->robj;
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if (!robj->pin_count) {
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if (lobj->wdomain) {
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robj->tobj.proposed_placement =
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radeon_object_flags_from_domain(lobj->wdomain);
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} else {
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robj->tobj.proposed_placement =
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radeon_object_flags_from_domain(lobj->rdomain);
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}
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r = ttm_buffer_object_validate(&robj->tobj,
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robj->tobj.proposed_placement,
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true, false);
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if (unlikely(r)) {
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DRM_ERROR("radeon: failed to validate.\n");
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return r;
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}
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radeon_object_gpu_addr(robj);
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}
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lobj->gpu_offset = robj->gpu_addr;
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lobj->tiling_flags = robj->tiling_flags;
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if (fence) {
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old_fence = (struct radeon_fence *)robj->tobj.sync_obj;
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robj->tobj.sync_obj = radeon_fence_ref(fence);
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robj->tobj.sync_obj_arg = NULL;
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}
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if (old_fence) {
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radeon_fence_unref(&old_fence);
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}
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}
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return 0;
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}
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void radeon_object_list_unvalidate(struct list_head *head)
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{
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struct radeon_object_list *lobj;
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struct radeon_fence *old_fence = NULL;
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struct list_head *i;
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list_for_each(i, head) {
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lobj = list_entry(i, struct radeon_object_list, list);
|
|
old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj;
|
|
lobj->robj->tobj.sync_obj = NULL;
|
|
if (old_fence) {
|
|
radeon_fence_unref(&old_fence);
|
|
}
|
|
}
|
|
radeon_object_list_unreserve(head);
|
|
}
|
|
|
|
void radeon_object_list_clean(struct list_head *head)
|
|
{
|
|
radeon_object_list_unreserve(head);
|
|
}
|
|
|
|
int radeon_object_fbdev_mmap(struct radeon_object *robj,
|
|
struct vm_area_struct *vma)
|
|
{
|
|
return ttm_fbdev_mmap(vma, &robj->tobj);
|
|
}
|
|
|
|
unsigned long radeon_object_size(struct radeon_object *robj)
|
|
{
|
|
return robj->tobj.num_pages << PAGE_SHIFT;
|
|
}
|
|
|
|
int radeon_object_get_surface_reg(struct radeon_object *robj)
|
|
{
|
|
struct radeon_device *rdev = robj->rdev;
|
|
struct radeon_surface_reg *reg;
|
|
struct radeon_object *old_object;
|
|
int steal;
|
|
int i;
|
|
|
|
if (!robj->tiling_flags)
|
|
return 0;
|
|
|
|
if (robj->surface_reg >= 0) {
|
|
reg = &rdev->surface_regs[robj->surface_reg];
|
|
i = robj->surface_reg;
|
|
goto out;
|
|
}
|
|
|
|
steal = -1;
|
|
for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
|
|
|
|
reg = &rdev->surface_regs[i];
|
|
if (!reg->robj)
|
|
break;
|
|
|
|
old_object = reg->robj;
|
|
if (old_object->pin_count == 0)
|
|
steal = i;
|
|
}
|
|
|
|
/* if we are all out */
|
|
if (i == RADEON_GEM_MAX_SURFACES) {
|
|
if (steal == -1)
|
|
return -ENOMEM;
|
|
/* find someone with a surface reg and nuke their BO */
|
|
reg = &rdev->surface_regs[steal];
|
|
old_object = reg->robj;
|
|
/* blow away the mapping */
|
|
DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
|
|
ttm_bo_unmap_virtual(&old_object->tobj);
|
|
old_object->surface_reg = -1;
|
|
i = steal;
|
|
}
|
|
|
|
robj->surface_reg = i;
|
|
reg->robj = robj;
|
|
|
|
out:
|
|
radeon_set_surface_reg(rdev, i, robj->tiling_flags, robj->pitch,
|
|
robj->tobj.mem.mm_node->start << PAGE_SHIFT,
|
|
robj->tobj.num_pages << PAGE_SHIFT);
|
|
return 0;
|
|
}
|
|
|
|
void radeon_object_clear_surface_reg(struct radeon_object *robj)
|
|
{
|
|
struct radeon_device *rdev = robj->rdev;
|
|
struct radeon_surface_reg *reg;
|
|
|
|
if (robj->surface_reg == -1)
|
|
return;
|
|
|
|
reg = &rdev->surface_regs[robj->surface_reg];
|
|
radeon_clear_surface_reg(rdev, robj->surface_reg);
|
|
|
|
reg->robj = NULL;
|
|
robj->surface_reg = -1;
|
|
}
|
|
|
|
void radeon_object_set_tiling_flags(struct radeon_object *robj,
|
|
uint32_t tiling_flags, uint32_t pitch)
|
|
{
|
|
robj->tiling_flags = tiling_flags;
|
|
robj->pitch = pitch;
|
|
}
|
|
|
|
void radeon_object_get_tiling_flags(struct radeon_object *robj,
|
|
uint32_t *tiling_flags,
|
|
uint32_t *pitch)
|
|
{
|
|
if (tiling_flags)
|
|
*tiling_flags = robj->tiling_flags;
|
|
if (pitch)
|
|
*pitch = robj->pitch;
|
|
}
|
|
|
|
int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
|
|
bool force_drop)
|
|
{
|
|
if (!(robj->tiling_flags & RADEON_TILING_SURFACE))
|
|
return 0;
|
|
|
|
if (force_drop) {
|
|
radeon_object_clear_surface_reg(robj);
|
|
return 0;
|
|
}
|
|
|
|
if (robj->tobj.mem.mem_type != TTM_PL_VRAM) {
|
|
if (!has_moved)
|
|
return 0;
|
|
|
|
if (robj->surface_reg >= 0)
|
|
radeon_object_clear_surface_reg(robj);
|
|
return 0;
|
|
}
|
|
|
|
if ((robj->surface_reg >= 0) && !has_moved)
|
|
return 0;
|
|
|
|
return radeon_object_get_surface_reg(robj);
|
|
}
|
|
|
|
void radeon_bo_move_notify(struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *mem)
|
|
{
|
|
struct radeon_object *robj = container_of(bo, struct radeon_object, tobj);
|
|
radeon_object_check_tiling(robj, 0, 1);
|
|
}
|
|
|
|
void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
{
|
|
struct radeon_object *robj = container_of(bo, struct radeon_object, tobj);
|
|
radeon_object_check_tiling(robj, 0, 0);
|
|
}
|