![Jerome Glisse](/assets/img/avatar_default.png)
Convert the rv515 asic support to new init path also add an explanation in radeon.h about the new init path. There is also few cleanups associated with this change (others asic calling rv515 helper functions). Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
651 lines
22 KiB
C
651 lines
22 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "drmP.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "rs690r.h"
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#include "atom.h"
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#include "atom-bits.h"
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/* rs690,rs740 depends on : */
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void r100_hdp_reset(struct radeon_device *rdev);
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int r300_mc_wait_for_idle(struct radeon_device *rdev);
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void r420_pipes_init(struct radeon_device *rdev);
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void rs400_gart_disable(struct radeon_device *rdev);
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int rs400_gart_enable(struct radeon_device *rdev);
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void rs400_gart_adjust_size(struct radeon_device *rdev);
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void rs600_mc_disable_clients(struct radeon_device *rdev);
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/* This files gather functions specifics to :
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* rs690,rs740
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*
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* Some of these functions might be used by newer ASICs.
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*/
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void rs690_gpu_init(struct radeon_device *rdev);
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int rs690_mc_wait_for_idle(struct radeon_device *rdev);
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/*
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* MC functions.
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*/
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int rs690_mc_init(struct radeon_device *rdev)
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{
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uint32_t tmp;
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int r;
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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rs690_gpu_init(rdev);
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rs400_gart_disable(rdev);
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/* Setup GPU memory space */
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rdev->mc.gtt_location = rdev->mc.mc_vram_size;
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rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
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rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
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rdev->mc.vram_location = 0xFFFFFFFFUL;
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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/* Program GPU memory space */
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rs600_mc_disable_clients(rdev);
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if (rs690_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
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tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16);
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tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16);
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WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp);
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/* FIXME: Does this reg exist on RS480,RS740 ? */
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WREG32(0x310, rdev->mc.vram_location);
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WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
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return 0;
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}
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void rs690_mc_fini(struct radeon_device *rdev)
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{
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}
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/*
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* Global GPU functions
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*/
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int rs690_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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uint32_t tmp;
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32_MC(RS690_MC_STATUS);
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if (tmp & RS690_MC_STATUS_IDLE) {
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return 0;
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}
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DRM_UDELAY(1);
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}
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return -1;
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}
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void rs690_errata(struct radeon_device *rdev)
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{
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rdev->pll_errata = 0;
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}
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void rs690_gpu_init(struct radeon_device *rdev)
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{
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/* FIXME: HDP same place on rs690 ? */
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r100_hdp_reset(rdev);
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rv515_vga_render_disable(rdev);
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/* FIXME: is this correct ? */
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r420_pipes_init(rdev);
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if (rs690_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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}
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/*
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* VRAM info.
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*/
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void rs690_pm_info(struct radeon_device *rdev)
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{
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int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
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struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
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struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
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void *ptr;
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uint16_t data_offset;
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uint8_t frev, crev;
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fixed20_12 tmp;
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atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
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&frev, &crev, &data_offset);
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ptr = rdev->mode_info.atom_context->bios + data_offset;
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info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
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info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
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/* Get various system informations from bios */
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switch (crev) {
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case 1:
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tmp.full = rfixed_const(100);
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rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
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rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
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rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
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rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
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break;
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case 2:
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tmp.full = rfixed_const(100);
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rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
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rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
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rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
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rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
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rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
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rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
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break;
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default:
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tmp.full = rfixed_const(100);
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/* We assume the slower possible clock ie worst case */
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/* DDR 333Mhz */
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rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
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/* FIXME: system clock ? */
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rdev->pm.igp_system_mclk.full = rfixed_const(100);
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rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
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rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
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rdev->pm.igp_ht_link_width.full = rfixed_const(8);
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DRM_ERROR("No integrated system info for your GPU, using safe default\n");
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break;
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}
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/* Compute various bandwidth */
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/* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
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tmp.full = rfixed_const(4);
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rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
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/* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
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* = ht_clk * ht_width / 5
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*/
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tmp.full = rfixed_const(5);
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rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
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rdev->pm.igp_ht_link_width);
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rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
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if (tmp.full < rdev->pm.max_bandwidth.full) {
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/* HT link is a limiting factor */
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rdev->pm.max_bandwidth.full = tmp.full;
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}
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/* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
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* = (sideport_clk * 14) / 10
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*/
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tmp.full = rfixed_const(14);
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rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
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tmp.full = rfixed_const(10);
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rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
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}
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void rs690_vram_info(struct radeon_device *rdev)
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{
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uint32_t tmp;
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fixed20_12 a;
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rs400_gart_adjust_size(rdev);
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/* DDR for all card after R300 & IGP */
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rdev->mc.vram_is_ddr = true;
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/* FIXME: is this correct for RS690/RS740 ? */
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tmp = RREG32(RADEON_MEM_CNTL);
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if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
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rdev->mc.vram_width = 128;
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} else {
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rdev->mc.vram_width = 64;
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}
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rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
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rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
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rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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rs690_pm_info(rdev);
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/* FIXME: we should enforce default clock in case GPU is not in
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* default setup
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*/
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a.full = rfixed_const(100);
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rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
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rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
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a.full = rfixed_const(16);
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/* core_bandwidth = sclk(Mhz) * 16 */
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rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
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}
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void rs690_line_buffer_adjust(struct radeon_device *rdev,
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struct drm_display_mode *mode1,
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struct drm_display_mode *mode2)
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{
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u32 tmp;
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/*
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* Line Buffer Setup
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* There is a single line buffer shared by both display controllers.
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* DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
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* the display controllers. The paritioning can either be done
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* manually or via one of four preset allocations specified in bits 1:0:
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* 0 - line buffer is divided in half and shared between crtc
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* 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
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* 2 - D1 gets the whole buffer
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* 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
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* Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual
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* allocation mode. In manual allocation mode, D1 always starts at 0,
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* D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
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*/
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tmp = RREG32(DC_LB_MEMORY_SPLIT) & ~DC_LB_MEMORY_SPLIT_MASK;
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tmp &= ~DC_LB_MEMORY_SPLIT_SHIFT_MODE;
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/* auto */
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if (mode1 && mode2) {
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if (mode1->hdisplay > mode2->hdisplay) {
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if (mode1->hdisplay > 2560)
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tmp |= DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
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else
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tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
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} else if (mode2->hdisplay > mode1->hdisplay) {
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if (mode2->hdisplay > 2560)
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tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
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else
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tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
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} else
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tmp |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
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} else if (mode1) {
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tmp |= DC_LB_MEMORY_SPLIT_D1_ONLY;
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} else if (mode2) {
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tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
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}
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WREG32(DC_LB_MEMORY_SPLIT, tmp);
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}
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struct rs690_watermark {
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u32 lb_request_fifo_depth;
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fixed20_12 num_line_pair;
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fixed20_12 estimated_width;
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fixed20_12 worst_case_latency;
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fixed20_12 consumption_rate;
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fixed20_12 active_time;
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fixed20_12 dbpp;
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fixed20_12 priority_mark_max;
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fixed20_12 priority_mark;
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fixed20_12 sclk;
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};
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void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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struct radeon_crtc *crtc,
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struct rs690_watermark *wm)
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{
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struct drm_display_mode *mode = &crtc->base.mode;
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fixed20_12 a, b, c;
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fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
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fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
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/* FIXME: detect IGP with sideport memory, i don't think there is any
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* such product available
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*/
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bool sideport = false;
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if (!crtc->base.enabled) {
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/* FIXME: wouldn't it better to set priority mark to maximum */
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wm->lb_request_fifo_depth = 4;
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return;
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}
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if (crtc->vsc.full > rfixed_const(2))
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wm->num_line_pair.full = rfixed_const(2);
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else
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wm->num_line_pair.full = rfixed_const(1);
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b.full = rfixed_const(mode->crtc_hdisplay);
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c.full = rfixed_const(256);
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a.full = rfixed_mul(wm->num_line_pair, b);
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request_fifo_depth.full = rfixed_div(a, c);
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if (a.full < rfixed_const(4)) {
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wm->lb_request_fifo_depth = 4;
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} else {
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wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
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}
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/* Determine consumption rate
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* pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
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* vtaps = number of vertical taps,
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* vsc = vertical scaling ratio, defined as source/destination
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* hsc = horizontal scaling ration, defined as source/destination
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*/
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a.full = rfixed_const(mode->clock);
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b.full = rfixed_const(1000);
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a.full = rfixed_div(a, b);
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pclk.full = rfixed_div(b, a);
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if (crtc->rmx_type != RMX_OFF) {
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b.full = rfixed_const(2);
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if (crtc->vsc.full > b.full)
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b.full = crtc->vsc.full;
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b.full = rfixed_mul(b, crtc->hsc);
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c.full = rfixed_const(2);
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b.full = rfixed_div(b, c);
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consumption_time.full = rfixed_div(pclk, b);
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} else {
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consumption_time.full = pclk.full;
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}
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a.full = rfixed_const(1);
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wm->consumption_rate.full = rfixed_div(a, consumption_time);
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/* Determine line time
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* LineTime = total time for one line of displayhtotal
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* LineTime = total number of horizontal pixels
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* pclk = pixel clock period(ns)
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*/
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a.full = rfixed_const(crtc->base.mode.crtc_htotal);
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line_time.full = rfixed_mul(a, pclk);
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/* Determine active time
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* ActiveTime = time of active region of display within one line,
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* hactive = total number of horizontal active pixels
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* htotal = total number of horizontal pixels
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*/
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a.full = rfixed_const(crtc->base.mode.crtc_htotal);
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b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
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wm->active_time.full = rfixed_mul(line_time, b);
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wm->active_time.full = rfixed_div(wm->active_time, a);
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/* Maximun bandwidth is the minimun bandwidth of all component */
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rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
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if (sideport) {
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if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
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rdev->pm.sideport_bandwidth.full)
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rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
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read_delay_latency.full = rfixed_const(370 * 800 * 1000);
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read_delay_latency.full = rfixed_div(read_delay_latency,
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rdev->pm.igp_sideport_mclk);
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} else {
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if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
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rdev->pm.k8_bandwidth.full)
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rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
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if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
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rdev->pm.ht_bandwidth.full)
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rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
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read_delay_latency.full = rfixed_const(5000);
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}
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/* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
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a.full = rfixed_const(16);
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rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
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a.full = rfixed_const(1000);
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rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
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/* Determine chunk time
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* ChunkTime = the time it takes the DCP to send one chunk of data
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* to the LB which consists of pipeline delay and inter chunk gap
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* sclk = system clock(ns)
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*/
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a.full = rfixed_const(256 * 13);
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chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
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a.full = rfixed_const(10);
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chunk_time.full = rfixed_div(chunk_time, a);
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/* Determine the worst case latency
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* NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
|
|
* WorstCaseLatency = worst case time from urgent to when the MC starts
|
|
* to return data
|
|
* READ_DELAY_IDLE_MAX = constant of 1us
|
|
* ChunkTime = time it takes the DCP to send one chunk of data to the LB
|
|
* which consists of pipeline delay and inter chunk gap
|
|
*/
|
|
if (rfixed_trunc(wm->num_line_pair) > 1) {
|
|
a.full = rfixed_const(3);
|
|
wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
|
|
wm->worst_case_latency.full += read_delay_latency.full;
|
|
} else {
|
|
a.full = rfixed_const(2);
|
|
wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
|
|
wm->worst_case_latency.full += read_delay_latency.full;
|
|
}
|
|
|
|
/* Determine the tolerable latency
|
|
* TolerableLatency = Any given request has only 1 line time
|
|
* for the data to be returned
|
|
* LBRequestFifoDepth = Number of chunk requests the LB can
|
|
* put into the request FIFO for a display
|
|
* LineTime = total time for one line of display
|
|
* ChunkTime = the time it takes the DCP to send one chunk
|
|
* of data to the LB which consists of
|
|
* pipeline delay and inter chunk gap
|
|
*/
|
|
if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
|
|
tolerable_latency.full = line_time.full;
|
|
} else {
|
|
tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
|
|
tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
|
|
tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
|
|
tolerable_latency.full = line_time.full - tolerable_latency.full;
|
|
}
|
|
/* We assume worst case 32bits (4 bytes) */
|
|
wm->dbpp.full = rfixed_const(4 * 8);
|
|
|
|
/* Determine the maximum priority mark
|
|
* width = viewport width in pixels
|
|
*/
|
|
a.full = rfixed_const(16);
|
|
wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
|
|
wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
|
|
|
|
/* Determine estimated width */
|
|
estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
|
|
estimated_width.full = rfixed_div(estimated_width, consumption_time);
|
|
if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
|
|
wm->priority_mark.full = rfixed_const(10);
|
|
} else {
|
|
a.full = rfixed_const(16);
|
|
wm->priority_mark.full = rfixed_div(estimated_width, a);
|
|
wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
|
|
}
|
|
}
|
|
|
|
void rs690_bandwidth_update(struct radeon_device *rdev)
|
|
{
|
|
struct drm_display_mode *mode0 = NULL;
|
|
struct drm_display_mode *mode1 = NULL;
|
|
struct rs690_watermark wm0;
|
|
struct rs690_watermark wm1;
|
|
u32 tmp;
|
|
fixed20_12 priority_mark02, priority_mark12, fill_rate;
|
|
fixed20_12 a, b;
|
|
|
|
if (rdev->mode_info.crtcs[0]->base.enabled)
|
|
mode0 = &rdev->mode_info.crtcs[0]->base.mode;
|
|
if (rdev->mode_info.crtcs[1]->base.enabled)
|
|
mode1 = &rdev->mode_info.crtcs[1]->base.mode;
|
|
/*
|
|
* Set display0/1 priority up in the memory controller for
|
|
* modes if the user specifies HIGH for displaypriority
|
|
* option.
|
|
*/
|
|
if (rdev->disp_priority == 2) {
|
|
tmp = RREG32_MC(MC_INIT_MISC_LAT_TIMER);
|
|
tmp &= ~MC_DISP1R_INIT_LAT_MASK;
|
|
tmp &= ~MC_DISP0R_INIT_LAT_MASK;
|
|
if (mode1)
|
|
tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
|
|
if (mode0)
|
|
tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
|
|
WREG32_MC(MC_INIT_MISC_LAT_TIMER, tmp);
|
|
}
|
|
rs690_line_buffer_adjust(rdev, mode0, mode1);
|
|
|
|
if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
|
|
WREG32(DCP_CONTROL, 0);
|
|
if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
|
|
WREG32(DCP_CONTROL, 2);
|
|
|
|
rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
|
|
rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
|
|
|
|
tmp = (wm0.lb_request_fifo_depth - 1);
|
|
tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
|
|
WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
|
|
|
|
if (mode0 && mode1) {
|
|
if (rfixed_trunc(wm0.dbpp) > 64)
|
|
a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
|
|
else
|
|
a.full = wm0.num_line_pair.full;
|
|
if (rfixed_trunc(wm1.dbpp) > 64)
|
|
b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
|
|
else
|
|
b.full = wm1.num_line_pair.full;
|
|
a.full += b.full;
|
|
fill_rate.full = rfixed_div(wm0.sclk, a);
|
|
if (wm0.consumption_rate.full > fill_rate.full) {
|
|
b.full = wm0.consumption_rate.full - fill_rate.full;
|
|
b.full = rfixed_mul(b, wm0.active_time);
|
|
a.full = rfixed_mul(wm0.worst_case_latency,
|
|
wm0.consumption_rate);
|
|
a.full = a.full + b.full;
|
|
b.full = rfixed_const(16 * 1000);
|
|
priority_mark02.full = rfixed_div(a, b);
|
|
} else {
|
|
a.full = rfixed_mul(wm0.worst_case_latency,
|
|
wm0.consumption_rate);
|
|
b.full = rfixed_const(16 * 1000);
|
|
priority_mark02.full = rfixed_div(a, b);
|
|
}
|
|
if (wm1.consumption_rate.full > fill_rate.full) {
|
|
b.full = wm1.consumption_rate.full - fill_rate.full;
|
|
b.full = rfixed_mul(b, wm1.active_time);
|
|
a.full = rfixed_mul(wm1.worst_case_latency,
|
|
wm1.consumption_rate);
|
|
a.full = a.full + b.full;
|
|
b.full = rfixed_const(16 * 1000);
|
|
priority_mark12.full = rfixed_div(a, b);
|
|
} else {
|
|
a.full = rfixed_mul(wm1.worst_case_latency,
|
|
wm1.consumption_rate);
|
|
b.full = rfixed_const(16 * 1000);
|
|
priority_mark12.full = rfixed_div(a, b);
|
|
}
|
|
if (wm0.priority_mark.full > priority_mark02.full)
|
|
priority_mark02.full = wm0.priority_mark.full;
|
|
if (rfixed_trunc(priority_mark02) < 0)
|
|
priority_mark02.full = 0;
|
|
if (wm0.priority_mark_max.full > priority_mark02.full)
|
|
priority_mark02.full = wm0.priority_mark_max.full;
|
|
if (wm1.priority_mark.full > priority_mark12.full)
|
|
priority_mark12.full = wm1.priority_mark.full;
|
|
if (rfixed_trunc(priority_mark12) < 0)
|
|
priority_mark12.full = 0;
|
|
if (wm1.priority_mark_max.full > priority_mark12.full)
|
|
priority_mark12.full = wm1.priority_mark_max.full;
|
|
WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
|
|
WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
|
|
WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
|
|
WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
|
|
} else if (mode0) {
|
|
if (rfixed_trunc(wm0.dbpp) > 64)
|
|
a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
|
|
else
|
|
a.full = wm0.num_line_pair.full;
|
|
fill_rate.full = rfixed_div(wm0.sclk, a);
|
|
if (wm0.consumption_rate.full > fill_rate.full) {
|
|
b.full = wm0.consumption_rate.full - fill_rate.full;
|
|
b.full = rfixed_mul(b, wm0.active_time);
|
|
a.full = rfixed_mul(wm0.worst_case_latency,
|
|
wm0.consumption_rate);
|
|
a.full = a.full + b.full;
|
|
b.full = rfixed_const(16 * 1000);
|
|
priority_mark02.full = rfixed_div(a, b);
|
|
} else {
|
|
a.full = rfixed_mul(wm0.worst_case_latency,
|
|
wm0.consumption_rate);
|
|
b.full = rfixed_const(16 * 1000);
|
|
priority_mark02.full = rfixed_div(a, b);
|
|
}
|
|
if (wm0.priority_mark.full > priority_mark02.full)
|
|
priority_mark02.full = wm0.priority_mark.full;
|
|
if (rfixed_trunc(priority_mark02) < 0)
|
|
priority_mark02.full = 0;
|
|
if (wm0.priority_mark_max.full > priority_mark02.full)
|
|
priority_mark02.full = wm0.priority_mark_max.full;
|
|
WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
|
|
WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
|
|
WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
|
|
WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
|
|
} else {
|
|
if (rfixed_trunc(wm1.dbpp) > 64)
|
|
a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
|
|
else
|
|
a.full = wm1.num_line_pair.full;
|
|
fill_rate.full = rfixed_div(wm1.sclk, a);
|
|
if (wm1.consumption_rate.full > fill_rate.full) {
|
|
b.full = wm1.consumption_rate.full - fill_rate.full;
|
|
b.full = rfixed_mul(b, wm1.active_time);
|
|
a.full = rfixed_mul(wm1.worst_case_latency,
|
|
wm1.consumption_rate);
|
|
a.full = a.full + b.full;
|
|
b.full = rfixed_const(16 * 1000);
|
|
priority_mark12.full = rfixed_div(a, b);
|
|
} else {
|
|
a.full = rfixed_mul(wm1.worst_case_latency,
|
|
wm1.consumption_rate);
|
|
b.full = rfixed_const(16 * 1000);
|
|
priority_mark12.full = rfixed_div(a, b);
|
|
}
|
|
if (wm1.priority_mark.full > priority_mark12.full)
|
|
priority_mark12.full = wm1.priority_mark.full;
|
|
if (rfixed_trunc(priority_mark12) < 0)
|
|
priority_mark12.full = 0;
|
|
if (wm1.priority_mark_max.full > priority_mark12.full)
|
|
priority_mark12.full = wm1.priority_mark_max.full;
|
|
WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
|
|
WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
|
|
WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
|
|
WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Indirect registers accessor
|
|
*/
|
|
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
|
|
{
|
|
uint32_t r;
|
|
|
|
WREG32(RS690_MC_INDEX, (reg & RS690_MC_INDEX_MASK));
|
|
r = RREG32(RS690_MC_DATA);
|
|
WREG32(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
|
|
return r;
|
|
}
|
|
|
|
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
|
{
|
|
WREG32(RS690_MC_INDEX,
|
|
RS690_MC_INDEX_WR_EN | ((reg) & RS690_MC_INDEX_MASK));
|
|
WREG32(RS690_MC_DATA, v);
|
|
WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
|
|
}
|