127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/*
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* Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*!
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* @file linux/mxc_dcic.h
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*
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* @brief Global header file for the MXC DCIC driver
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*
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* @ingroup MXC DCIC
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*/
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#ifndef __LINUX_DCIC_H__
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#define __LINUX_DCIC_H__
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#include <uapi/linux/mxc_dcic.h>
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#define DCICC_IC_ENABLE 0x1
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#define DCICC_IC_DISABLE 0x0
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#define DCICC_IC_MASK 0x1
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#define DCICC_DE_ACTIVE_HIGH 0
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#define DCICC_DE_ACTIVE_LOW (0x1 << 4)
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#define DCICC_DE_ACTIVE_MASK (0x1 << 4)
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#define DCICC_HSYNC_POL_ACTIVE_HIGH 0
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#define DCICC_HSYNC_POL_ACTIVE_LOW (0x1 << 5)
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#define DCICC_HSYNC_POL_ACTIVE_MASK (0x1 << 5)
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#define DCICC_VSYNC_POL_ACTIVE_HIGH 0
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#define DCICC_VSYNC_POL_ACTIVE_LOW (0x1 << 6)
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#define DCICC_VSYNC_POL_ACTIVE_MASK (0x1 << 6)
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#define DCICC_CLK_POL_NO_INVERTED 0
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#define DCICC_CLK_POL_INVERTED (0x1 << 7)
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#define DCICC_CLK_POL_INVERTED_MASK (0x1 << 7)
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#define DCICIC_ERROR_INT_DISABLE 1
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#define DCICIC_ERROR_INT_ENABLE 0
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#define DCICIC_ERROR_INT_MASK_MASK 1
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#define DCICIC_FUN_INT_DISABLE (0x1 << 1)
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#define DCICIC_FUN_INT_ENABLE 0
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#define DCICIC_FUN_INT_MASK (0x1 << 1)
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#define DCICIC_FREEZE_MASK_CHANGED 0
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#define DCICIC_FREEZE_MASK_FORZEN (0x1 << 3)
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#define DCICIC_FREEZE_MASK_MASK (0x1 << 3)
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#define DCICIC_EXT_SIG_EX_DISABLE 0
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#define DCICIC_EXT_SIG_EN_ENABLE (0x1 << 16)
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#define DCICIC_EXT_SIG_EN_MASK (0x1 << 16)
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#define DCICS_ROI_MATCH_STAT_MASK 0xFFFF
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#define DCICS_EI_STAT_PENDING (0x1 << 16)
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#define DCICS_EI_STAT_NO_PENDING 0
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#define DCICS_FI_STAT_PENDING (0x1 << 17)
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#define DCICS_FI_STAT_NO_PENDING 0
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#define DCICRC_ROI_START_OFFSET_X_MASK 0x1FFF
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#define DCICRC_ROI_START_OFFSET_X_SHIFT 0
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#define DCICRC_ROI_START_OFFSET_Y_MASK (0xFFF << 16)
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#define DCICRC_ROI_START_OFFSET_Y_SHIFT 16
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#define DCICRC_ROI_CHANGED 0
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#define DCICRC_ROI_FROZEN (0x1 << 30)
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#define DCICRC_ROI_ENABLE (0x1 << 31)
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#define DCICRC_ROI_DISABLE 0
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#define DCICRS_ROI_END_OFFSET_X_MASK 0x1FFF
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#define DCICRS_ROI_END_OFFSET_X_SHIFT 0
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#define DCICRS_ROI_END_OFFSET_Y_MASK (0xFFF << 16)
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#define DCICRS_ROI_END_OFFSET_Y_SHIFT 16
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struct roi_regs {
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u32 dcicrc;
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u32 dcicrs;
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u32 dcicrrs;
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u32 dcicrcs;
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};
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struct dcic_regs {
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u32 dcicc;
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u32 dcicic;
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u32 dcics;
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u32 dcic_reserved;
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struct roi_regs ROI[16];
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};
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struct dcic_mux {
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char dcic[16];
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u32 val;
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};
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struct bus_mux {
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char name[16];
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int reg;
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int shift;
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int mask;
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int dcic_mux_num;
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const struct dcic_mux *dcics;
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};
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struct dcic_info {
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int bus_mux_num;
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const struct bus_mux *buses;
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};
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struct dcic_data {
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struct regmap *regmap;
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struct device *dev;
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struct dcic_regs *regs;
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const struct bus_mux *buses;
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u32 bus_n;
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u32 mux_n;
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struct clk *disp_axi_clk;
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struct clk *dcic_clk;
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struct mutex lock;
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struct completion roi_crc_comp;
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struct class *class;
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int major;
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struct cdev cdev; /* Char device structure */
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dev_t devt;
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unsigned int result;
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};
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#endif
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