71 lines
2.0 KiB
Plaintext
71 lines
2.0 KiB
Plaintext
/*
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* Copyright 2019 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* fec1 cannot attach to ethphy0 since the PHY address
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* conflict with ethphy2. So eth0 should not work.
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* There still enable fec1 to share the MDIO bus for fec2 due
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* to board limitation.
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*/
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&fec1 {
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/* PHY address should rework to 3 */
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phy-handle = <ðphy3>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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tja110x,refclk_in;
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/delete-property/ at803x,eee-disabled;
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/delete-property/ at803x,vddio-1p8v;
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};
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ethphy3: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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at803x,eee-disabled;
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at803x,vddio-1p8v;
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};
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};
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};
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&fec2 {
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pinctrl-0 = <&pinctrl_fec2_rmii>;
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clocks = <&enet1_lpcg 4>,
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<&enet1_lpcg 2>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>,
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<&enet1_lpcg 0>,
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<&enet1_lpcg 1>;
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phy-mode = "rmii";
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phy-handle = <ðphy2>;
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/delete-property/ phy-supply;
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};
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&iomuxc {
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pinctrl_fec2_rmii: fec2rmiigrp {
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fsl,pins = <
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IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT 0x06000020
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IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020
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IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020
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IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER 0x06000020
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IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020
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IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020
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IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020
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IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020
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>;
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};
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};
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