![David Woodhouse](/assets/img/avatar_default.png)
It'll take some work before this is really shippable. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
199 lines
5.4 KiB
C
199 lines
5.4 KiB
C
/*
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* NAND Flash Controller Device Driver
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* Copyright (c) 2009, Intel Corporation and its suppliers.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef _FLASH_INTERFACE_
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#define _FLASH_INTERFACE_
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#include "ffsport.h"
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#include "spectraswconfig.h"
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#define MAX_BYTE_VALUE 0xFF
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#define MAX_WORD_VALUE 0xFFFF
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#define MAX_U32_VALUE 0xFFFFFFFF
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#define MAX_BLOCKNODE_VALUE 0xFFFFFF
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#define DISCARD_BLOCK 0x800000
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#define SPARE_BLOCK 0x400000
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#define BAD_BLOCK 0xC00000
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#define UNHIT_CACHE_ITEM 0xFFFF
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#define NAND_CACHE_INIT_ADDR 0xffffffffffffffffULL
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#define IN_PROGRESS_BLOCK_TABLE 0x00
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#define CURRENT_BLOCK_TABLE 0x01
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#define BTSIG_OFFSET (0)
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#define BTSIG_BYTES (5)
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#define BTSIG_DELTA (3)
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#define MAX_READ_COUNTER 0x2710
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#define FIRST_BT_ID (1)
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#define LAST_BT_ID (254)
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#define BTBLOCK_INVAL (u32)(0xFFFFFFFF)
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struct device_info_tag {
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u16 wDeviceMaker;
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u16 wDeviceID;
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u32 wDeviceType;
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u32 wSpectraStartBlock;
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u32 wSpectraEndBlock;
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u32 wTotalBlocks;
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u16 wPagesPerBlock;
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u16 wPageSize;
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u16 wPageDataSize;
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u16 wPageSpareSize;
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u16 wNumPageSpareFlag;
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u16 wECCBytesPerSector;
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u32 wBlockSize;
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u32 wBlockDataSize;
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u32 wDataBlockNum;
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u8 bPlaneNum;
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u16 wDeviceMainAreaSize;
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u16 wDeviceSpareAreaSize;
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u16 wDevicesConnected;
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u16 wDeviceWidth;
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u16 wHWRevision;
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u16 wHWFeatures;
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u16 wONFIDevFeatures;
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u16 wONFIOptCommands;
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u16 wONFITimingMode;
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u16 wONFIPgmCacheTimingMode;
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u16 MLCDevice;
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u16 wSpareSkipBytes;
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u8 nBitsInPageNumber;
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u8 nBitsInPageDataSize;
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u8 nBitsInBlockDataSize;
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};
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extern struct device_info_tag DeviceInfo;
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/* Cache item format */
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struct flash_cache_item_tag {
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u64 address;
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u16 use_cnt;
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u16 changed;
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u8 *buf;
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};
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struct flash_cache_tag {
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u32 cache_item_size; /* Size in bytes of each cache item */
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u16 pages_per_item; /* How many NAND pages in each cache item */
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u16 LRU; /* No. of the least recently used cache item */
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struct flash_cache_item_tag array[CACHE_ITEM_NUM];
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};
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/*
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*Data structure for each list node of the managment table
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* used for the Level 2 Cache. Each node maps one logical NAND block.
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*/
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struct spectra_l2_cache_list {
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struct list_head list;
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u32 logical_blk_num; /* Logical block number */
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u32 pages_array[]; /* Page map array of this logical block.
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* Array index is the logical block number,
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* and for every item of this arry:
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* high 16 bit is index of the L2 cache block num,
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* low 16 bit is the phy page num
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* of the above L2 cache block.
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* This array will be kmalloc during run time.
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*/
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};
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struct spectra_l2_cache_info {
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u32 blk_array[BLK_NUM_FOR_L2_CACHE];
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u16 cur_blk_idx; /* idx to the phy block number of current using */
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u16 cur_page_num; /* pages number of current using */
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struct spectra_l2_cache_list table; /* First node of the table */
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};
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#define RESTORE_CACHE_ON_CDMA_CHAIN_FAILURE 1
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#if RESTORE_CACHE_ON_CDMA_CHAIN_FAILURE
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struct flash_cache_mod_item_tag {
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u64 address;
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u8 changed;
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};
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struct flash_cache_delta_list_tag {
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u8 item; /* used cache item */
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struct flash_cache_mod_item_tag cache;
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};
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#endif
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extern struct flash_cache_tag Cache;
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extern u8 *buf_read_page_main_spare;
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extern u8 *buf_write_page_main_spare;
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extern u8 *buf_read_page_spare;
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extern u8 *buf_get_bad_block;
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extern u8 *cdma_desc_buf;
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extern u8 *memcp_desc_buf;
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/* struture used for IndentfyDevice function */
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struct spectra_indentfy_dev_tag {
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u32 NumBlocks;
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u16 PagesPerBlock;
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u16 PageDataSize;
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u16 wECCBytesPerSector;
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u32 wDataBlockNum;
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};
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int GLOB_FTL_Flash_Init(void);
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int GLOB_FTL_Flash_Release(void);
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/*void GLOB_FTL_Erase_Flash(void);*/
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int GLOB_FTL_Block_Erase(u64 block_addr);
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int GLOB_FTL_Is_BadBlock(u32 block_num);
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int GLOB_FTL_IdentifyDevice(struct spectra_indentfy_dev_tag *dev_data);
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int GLOB_FTL_Event_Status(int *);
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u16 glob_ftl_execute_cmds(void);
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/*int FTL_Read_Disturbance(ADDRESSTYPE dwBlockAddr);*/
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int FTL_Read_Disturbance(u32 dwBlockAddr);
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/*Flash r/w based on cache*/
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int GLOB_FTL_Page_Read(u8 *read_data, u64 page_addr);
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int GLOB_FTL_Page_Write(u8 *write_data, u64 page_addr);
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int GLOB_FTL_Wear_Leveling(void);
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int GLOB_FTL_Flash_Format(void);
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int GLOB_FTL_Init(void);
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int GLOB_FTL_Flush_Cache(void);
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int GLOB_FTL_Garbage_Collection(void);
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int GLOB_FTL_BT_Garbage_Collection(void);
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void GLOB_FTL_Cache_Release(void);
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u8 *get_blk_table_start_addr(void);
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u8 *get_wear_leveling_table_start_addr(void);
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unsigned long get_blk_table_len(void);
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unsigned long get_wear_leveling_table_len(void);
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#if DEBUG_BNDRY
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void debug_boundary_lineno_error(int chnl, int limit, int no, int lineno,
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char *filename);
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#define debug_boundary_error(chnl, limit, no) debug_boundary_lineno_error(chnl,\
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limit, no, __LINE__, __FILE__)
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#else
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#define debug_boundary_error(chnl, limit, no) ;
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#endif
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#endif /*_FLASH_INTERFACE_*/
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