![Tejun Heo](/assets/img/avatar_default.png)
->post_internal_cmd is simplified EH for internal commands. Its primary mission is to stop the controller such that no rogue memory access or other activities occur after the internal command is released. It may provide error diagnostics by setting qc->err_mask but this hasn't been a requirement. To ignore SETXFER failure for CFA devices, libata needs to know whether a command was failed by the device or for any other reason. ie. internal command needs to get AC_ERR_DEV right. This patch makes the following changes to AC_ERR_DEV handling and ->post_internal_cmd semantics to accomodate this need and simplify callback implementation. 1. As long as the correct bits in the result TF registers are set, there is no need to set AC_ERR_DEV explicitly. libata EH core takes care of that for both normal and internal commands. 2. The only requirement for ->post_internal_cmd() is to put the controller into quiescent state. It needs not to set any err_mask. 3. ata_exec_internal_sg() performs minimal error analysis such that AC_ERR_DEV is automatically set as long as result_tf is filled correctly. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
1048 lines
28 KiB
C
1048 lines
28 KiB
C
/*
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* sata_promise.c - Promise SATA
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003-2004 Red Hat, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware information only available under NDA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_cmnd.h>
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#include <linux/libata.h>
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#include "sata_promise.h"
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#define DRV_NAME "sata_promise"
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#define DRV_VERSION "2.05"
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enum {
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PDC_MMIO_BAR = 3,
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/* register offsets */
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PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
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PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
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PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
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PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
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PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
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PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
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PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
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PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
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PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
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PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
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PDC_FLASH_CTL = 0x44, /* Flash control register */
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PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
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PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
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PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
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PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
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PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
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PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
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/* PDC_GLOBAL_CTL bit definitions */
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PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
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PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
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PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
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PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
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PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
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PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
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PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
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PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
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PDC_DRIVE_ERR = (1 << 21), /* drive error */
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PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
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PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
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PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
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PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR,
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PDC_ERR_MASK = (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR
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| PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR
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| PDC1_ERR_MASK | PDC2_ERR_MASK),
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board_2037x = 0, /* FastTrak S150 TX2plus */
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board_20319 = 1, /* FastTrak S150 TX4 */
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board_20619 = 2, /* FastTrak TX4000 */
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board_2057x = 3, /* SATAII150 Tx2plus */
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board_40518 = 4, /* SATAII150 Tx4 */
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PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
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/* Sequence counter control registers bit definitions */
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PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
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/* Feature register values */
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PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
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PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
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/* Device/Head register values */
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PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
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/* PDC_CTLSTAT bit definitions */
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PDC_DMA_ENABLE = (1 << 7),
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PDC_IRQ_DISABLE = (1 << 10),
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PDC_RESET = (1 << 11), /* HDMA reset */
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PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO |
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ATA_FLAG_PIO_POLLING,
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/* hp->flags bits */
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PDC_FLAG_GEN_II = (1 << 0),
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};
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struct pdc_port_priv {
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u8 *pkt;
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dma_addr_t pkt_dma;
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};
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struct pdc_host_priv {
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unsigned long flags;
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unsigned long port_flags[ATA_MAX_PORTS];
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};
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static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
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static int pdc_port_start(struct ata_port *ap);
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static void pdc_qc_prep(struct ata_queued_cmd *qc);
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static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
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static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
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static void pdc_irq_clear(struct ata_port *ap);
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static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
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static void pdc_freeze(struct ata_port *ap);
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static void pdc_thaw(struct ata_port *ap);
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static void pdc_pata_error_handler(struct ata_port *ap);
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static void pdc_sata_error_handler(struct ata_port *ap);
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static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
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static int pdc_pata_cable_detect(struct ata_port *ap);
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static int pdc_sata_cable_detect(struct ata_port *ap);
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static struct scsi_host_template pdc_ata_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static const struct ata_port_operations pdc_sata_ops = {
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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.check_atapi_dma = pdc_check_atapi_dma,
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.qc_prep = pdc_qc_prep,
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.qc_issue = pdc_qc_issue_prot,
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.freeze = pdc_freeze,
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.thaw = pdc_thaw,
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.error_handler = pdc_sata_error_handler,
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.post_internal_cmd = pdc_post_internal_cmd,
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.cable_detect = pdc_sata_cable_detect,
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.data_xfer = ata_data_xfer,
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.irq_handler = pdc_interrupt,
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.irq_clear = pdc_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.scr_read = pdc_sata_scr_read,
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.scr_write = pdc_sata_scr_write,
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.port_start = pdc_port_start,
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};
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/* First-generation chips need a more restrictive ->check_atapi_dma op */
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static const struct ata_port_operations pdc_old_sata_ops = {
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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.check_atapi_dma = pdc_old_sata_check_atapi_dma,
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.qc_prep = pdc_qc_prep,
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.qc_issue = pdc_qc_issue_prot,
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.freeze = pdc_freeze,
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.thaw = pdc_thaw,
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.error_handler = pdc_sata_error_handler,
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.post_internal_cmd = pdc_post_internal_cmd,
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.cable_detect = pdc_sata_cable_detect,
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.data_xfer = ata_data_xfer,
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.irq_handler = pdc_interrupt,
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.irq_clear = pdc_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.scr_read = pdc_sata_scr_read,
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.scr_write = pdc_sata_scr_write,
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.port_start = pdc_port_start,
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};
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static const struct ata_port_operations pdc_pata_ops = {
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.port_disable = ata_port_disable,
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.tf_load = pdc_tf_load_mmio,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = pdc_exec_command_mmio,
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.dev_select = ata_std_dev_select,
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.check_atapi_dma = pdc_check_atapi_dma,
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.qc_prep = pdc_qc_prep,
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.qc_issue = pdc_qc_issue_prot,
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.freeze = pdc_freeze,
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.thaw = pdc_thaw,
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.error_handler = pdc_pata_error_handler,
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.post_internal_cmd = pdc_post_internal_cmd,
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.cable_detect = pdc_pata_cable_detect,
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.data_xfer = ata_data_xfer,
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.irq_handler = pdc_interrupt,
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.irq_clear = pdc_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = pdc_port_start,
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};
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static const struct ata_port_info pdc_port_info[] = {
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/* board_2037x */
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{
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.sht = &pdc_ata_sht,
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.flags = PDC_COMMON_FLAGS,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_old_sata_ops,
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},
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/* board_20319 */
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{
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.sht = &pdc_ata_sht,
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.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_old_sata_ops,
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},
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/* board_20619 */
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{
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.sht = &pdc_ata_sht,
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.flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_pata_ops,
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},
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/* board_2057x */
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{
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.sht = &pdc_ata_sht,
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.flags = PDC_COMMON_FLAGS,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_sata_ops,
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},
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/* board_40518 */
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{
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.sht = &pdc_ata_sht,
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.flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &pdc_sata_ops,
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},
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};
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static const struct pci_device_id pdc_ata_pci_tbl[] = {
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{ PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
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{ PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
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{ PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
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{ PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
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{ PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
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{ PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
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{ PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
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{ PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
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{ PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
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{ PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
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{ PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
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{ PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
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{ PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
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{ PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
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{ PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
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{ PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
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{ PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
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{ } /* terminate list */
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};
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static struct pci_driver pdc_ata_pci_driver = {
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.name = DRV_NAME,
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.id_table = pdc_ata_pci_tbl,
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.probe = pdc_ata_init_one,
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.remove = ata_pci_remove_one,
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};
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static int pdc_common_port_start(struct ata_port *ap)
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{
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struct device *dev = ap->host->dev;
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struct pdc_port_priv *pp;
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int rc;
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rc = ata_port_start(ap);
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if (rc)
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return rc;
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pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
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if (!pp)
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return -ENOMEM;
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pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
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if (!pp->pkt)
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return -ENOMEM;
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ap->private_data = pp;
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return 0;
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}
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static int pdc_sata_port_start(struct ata_port *ap)
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{
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struct pdc_host_priv *hp = ap->host->private_data;
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int rc;
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rc = pdc_common_port_start(ap);
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if (rc)
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return rc;
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/* fix up PHYMODE4 align timing */
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if (hp->flags & PDC_FLAG_GEN_II) {
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void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
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unsigned int tmp;
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tmp = readl(mmio + 0x014);
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tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
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writel(tmp, mmio + 0x014);
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}
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return 0;
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}
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static int pdc_port_start(struct ata_port *ap)
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{
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struct pdc_host_priv *hp = ap->host->private_data;
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/* fix up port flags and cable type for SATA+PATA chips */
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ap->flags |= hp->port_flags[ap->port_no];
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if (ap->flags & ATA_FLAG_SATA) {
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ap->cbl = ATA_CBL_SATA;
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return pdc_sata_port_start(ap);
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} else {
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ap->ops = &pdc_pata_ops;
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return pdc_common_port_start(ap);
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}
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}
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static void pdc_reset_port(struct ata_port *ap)
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{
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void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
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unsigned int i;
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u32 tmp;
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for (i = 11; i > 0; i--) {
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tmp = readl(mmio);
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if (tmp & PDC_RESET)
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break;
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|
|
udelay(100);
|
|
|
|
tmp |= PDC_RESET;
|
|
writel(tmp, mmio);
|
|
}
|
|
|
|
tmp &= ~PDC_RESET;
|
|
writel(tmp, mmio);
|
|
readl(mmio); /* flush */
|
|
}
|
|
|
|
static int pdc_pata_cable_detect(struct ata_port *ap)
|
|
{
|
|
u8 tmp;
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
|
|
|
|
tmp = readb(mmio);
|
|
if (tmp & 0x01)
|
|
return ATA_CBL_PATA40;
|
|
return ATA_CBL_PATA80;
|
|
}
|
|
|
|
static int pdc_sata_cable_detect(struct ata_port *ap)
|
|
{
|
|
return ATA_CBL_SATA;
|
|
}
|
|
|
|
static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
|
|
{
|
|
if (sc_reg > SCR_CONTROL)
|
|
return 0xffffffffU;
|
|
return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
|
|
}
|
|
|
|
|
|
static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
|
|
u32 val)
|
|
{
|
|
if (sc_reg > SCR_CONTROL)
|
|
return;
|
|
writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
|
|
}
|
|
|
|
static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
dma_addr_t sg_table = ap->prd_dma;
|
|
unsigned int cdb_len = qc->dev->cdb_len;
|
|
u8 *cdb = qc->cdb;
|
|
struct pdc_port_priv *pp = ap->private_data;
|
|
u8 *buf = pp->pkt;
|
|
u32 *buf32 = (u32 *) buf;
|
|
unsigned int dev_sel, feature, nbytes;
|
|
|
|
/* set control bits (byte 0), zero delay seq id (byte 3),
|
|
* and seq id (byte 2)
|
|
*/
|
|
switch (qc->tf.protocol) {
|
|
case ATA_PROT_ATAPI_DMA:
|
|
if (!(qc->tf.flags & ATA_TFLAG_WRITE))
|
|
buf32[0] = cpu_to_le32(PDC_PKT_READ);
|
|
else
|
|
buf32[0] = 0;
|
|
break;
|
|
case ATA_PROT_ATAPI_NODATA:
|
|
buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
|
|
break;
|
|
default:
|
|
BUG();
|
|
break;
|
|
}
|
|
buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
|
|
buf32[2] = 0; /* no next-packet */
|
|
|
|
/* select drive */
|
|
if (sata_scr_valid(ap)) {
|
|
dev_sel = PDC_DEVICE_SATA;
|
|
} else {
|
|
dev_sel = ATA_DEVICE_OBS;
|
|
if (qc->dev->devno != 0)
|
|
dev_sel |= ATA_DEV1;
|
|
}
|
|
buf[12] = (1 << 5) | ATA_REG_DEVICE;
|
|
buf[13] = dev_sel;
|
|
buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
|
|
buf[15] = dev_sel; /* once more, waiting for BSY to clear */
|
|
|
|
buf[16] = (1 << 5) | ATA_REG_NSECT;
|
|
buf[17] = 0x00;
|
|
buf[18] = (1 << 5) | ATA_REG_LBAL;
|
|
buf[19] = 0x00;
|
|
|
|
/* set feature and byte counter registers */
|
|
if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
|
|
feature = PDC_FEATURE_ATAPI_PIO;
|
|
/* set byte counter register to real transfer byte count */
|
|
nbytes = qc->nbytes;
|
|
if (nbytes > 0xffff)
|
|
nbytes = 0xffff;
|
|
} else {
|
|
feature = PDC_FEATURE_ATAPI_DMA;
|
|
/* set byte counter register to 0 */
|
|
nbytes = 0;
|
|
}
|
|
buf[20] = (1 << 5) | ATA_REG_FEATURE;
|
|
buf[21] = feature;
|
|
buf[22] = (1 << 5) | ATA_REG_BYTEL;
|
|
buf[23] = nbytes & 0xFF;
|
|
buf[24] = (1 << 5) | ATA_REG_BYTEH;
|
|
buf[25] = (nbytes >> 8) & 0xFF;
|
|
|
|
/* send ATAPI packet command 0xA0 */
|
|
buf[26] = (1 << 5) | ATA_REG_CMD;
|
|
buf[27] = ATA_CMD_PACKET;
|
|
|
|
/* select drive and check DRQ */
|
|
buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
|
|
buf[29] = dev_sel;
|
|
|
|
/* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
|
|
BUG_ON(cdb_len & ~0x1E);
|
|
|
|
/* append the CDB as the final part */
|
|
buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
|
|
memcpy(buf+31, cdb, cdb_len);
|
|
}
|
|
|
|
static void pdc_qc_prep(struct ata_queued_cmd *qc)
|
|
{
|
|
struct pdc_port_priv *pp = qc->ap->private_data;
|
|
unsigned int i;
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
switch (qc->tf.protocol) {
|
|
case ATA_PROT_DMA:
|
|
ata_qc_prep(qc);
|
|
/* fall through */
|
|
|
|
case ATA_PROT_NODATA:
|
|
i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
|
|
qc->dev->devno, pp->pkt);
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_LBA48)
|
|
i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
|
|
else
|
|
i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
|
|
|
|
pdc_pkt_footer(&qc->tf, pp->pkt, i);
|
|
break;
|
|
|
|
case ATA_PROT_ATAPI:
|
|
ata_qc_prep(qc);
|
|
break;
|
|
|
|
case ATA_PROT_ATAPI_DMA:
|
|
ata_qc_prep(qc);
|
|
/*FALLTHROUGH*/
|
|
case ATA_PROT_ATAPI_NODATA:
|
|
pdc_atapi_pkt(qc);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void pdc_freeze(struct ata_port *ap)
|
|
{
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
|
|
u32 tmp;
|
|
|
|
tmp = readl(mmio + PDC_CTLSTAT);
|
|
tmp |= PDC_IRQ_DISABLE;
|
|
tmp &= ~PDC_DMA_ENABLE;
|
|
writel(tmp, mmio + PDC_CTLSTAT);
|
|
readl(mmio + PDC_CTLSTAT); /* flush */
|
|
}
|
|
|
|
static void pdc_thaw(struct ata_port *ap)
|
|
{
|
|
void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
|
|
u32 tmp;
|
|
|
|
/* clear IRQ */
|
|
readl(mmio + PDC_INT_SEQMASK);
|
|
|
|
/* turn IRQ back on */
|
|
tmp = readl(mmio + PDC_CTLSTAT);
|
|
tmp &= ~PDC_IRQ_DISABLE;
|
|
writel(tmp, mmio + PDC_CTLSTAT);
|
|
readl(mmio + PDC_CTLSTAT); /* flush */
|
|
}
|
|
|
|
static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
|
|
{
|
|
if (!(ap->pflags & ATA_PFLAG_FROZEN))
|
|
pdc_reset_port(ap);
|
|
|
|
/* perform recovery */
|
|
ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
|
|
ata_std_postreset);
|
|
}
|
|
|
|
static void pdc_pata_error_handler(struct ata_port *ap)
|
|
{
|
|
pdc_common_error_handler(ap, NULL);
|
|
}
|
|
|
|
static void pdc_sata_error_handler(struct ata_port *ap)
|
|
{
|
|
pdc_common_error_handler(ap, sata_std_hardreset);
|
|
}
|
|
|
|
static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
/* make DMA engine forget about the failed command */
|
|
if (qc->flags & ATA_QCFLAG_FAILED)
|
|
pdc_reset_port(ap);
|
|
}
|
|
|
|
static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
|
|
u32 port_status, u32 err_mask)
|
|
{
|
|
struct ata_eh_info *ehi = &ap->eh_info;
|
|
unsigned int ac_err_mask = 0;
|
|
|
|
ata_ehi_clear_desc(ehi);
|
|
ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
|
|
port_status &= err_mask;
|
|
|
|
if (port_status & PDC_DRIVE_ERR)
|
|
ac_err_mask |= AC_ERR_DEV;
|
|
if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
|
|
ac_err_mask |= AC_ERR_HSM;
|
|
if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
|
|
ac_err_mask |= AC_ERR_ATA_BUS;
|
|
if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
|
|
| PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
|
|
ac_err_mask |= AC_ERR_HOST_BUS;
|
|
|
|
if (sata_scr_valid(ap))
|
|
ehi->serror |= pdc_sata_scr_read(ap, SCR_ERROR);
|
|
|
|
qc->err_mask |= ac_err_mask;
|
|
|
|
pdc_reset_port(ap);
|
|
}
|
|
|
|
static inline unsigned int pdc_host_intr( struct ata_port *ap,
|
|
struct ata_queued_cmd *qc)
|
|
{
|
|
unsigned int handled = 0;
|
|
void __iomem *port_mmio = ap->ioaddr.cmd_addr;
|
|
struct pdc_host_priv *hp = ap->host->private_data;
|
|
u32 port_status, err_mask;
|
|
|
|
err_mask = PDC_ERR_MASK;
|
|
if (hp->flags & PDC_FLAG_GEN_II)
|
|
err_mask &= ~PDC1_ERR_MASK;
|
|
else
|
|
err_mask &= ~PDC2_ERR_MASK;
|
|
port_status = readl(port_mmio + PDC_GLOBAL_CTL);
|
|
if (unlikely(port_status & err_mask)) {
|
|
pdc_error_intr(ap, qc, port_status, err_mask);
|
|
return 1;
|
|
}
|
|
|
|
switch (qc->tf.protocol) {
|
|
case ATA_PROT_DMA:
|
|
case ATA_PROT_NODATA:
|
|
case ATA_PROT_ATAPI_DMA:
|
|
case ATA_PROT_ATAPI_NODATA:
|
|
qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
|
|
ata_qc_complete(qc);
|
|
handled = 1;
|
|
break;
|
|
|
|
default:
|
|
ap->stats.idle_irq++;
|
|
break;
|
|
}
|
|
|
|
return handled;
|
|
}
|
|
|
|
static void pdc_irq_clear(struct ata_port *ap)
|
|
{
|
|
struct ata_host *host = ap->host;
|
|
void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
|
|
|
|
readl(mmio + PDC_INT_SEQMASK);
|
|
}
|
|
|
|
static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
|
|
{
|
|
struct ata_host *host = dev_instance;
|
|
struct ata_port *ap;
|
|
u32 mask = 0;
|
|
unsigned int i, tmp;
|
|
unsigned int handled = 0;
|
|
void __iomem *mmio_base;
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
if (!host || !host->iomap[PDC_MMIO_BAR]) {
|
|
VPRINTK("QUICK EXIT\n");
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
mmio_base = host->iomap[PDC_MMIO_BAR];
|
|
|
|
/* reading should also clear interrupts */
|
|
mask = readl(mmio_base + PDC_INT_SEQMASK);
|
|
|
|
if (mask == 0xffffffff) {
|
|
VPRINTK("QUICK EXIT 2\n");
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
mask &= 0xffff; /* only 16 tags possible */
|
|
if (!mask) {
|
|
VPRINTK("QUICK EXIT 3\n");
|
|
goto done_irq;
|
|
}
|
|
|
|
writel(mask, mmio_base + PDC_INT_SEQMASK);
|
|
|
|
for (i = 0; i < host->n_ports; i++) {
|
|
VPRINTK("port %u\n", i);
|
|
ap = host->ports[i];
|
|
tmp = mask & (1 << (i + 1));
|
|
if (tmp && ap &&
|
|
!(ap->flags & ATA_FLAG_DISABLED)) {
|
|
struct ata_queued_cmd *qc;
|
|
|
|
qc = ata_qc_from_tag(ap, ap->active_tag);
|
|
if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
|
|
handled += pdc_host_intr(ap, qc);
|
|
}
|
|
}
|
|
|
|
VPRINTK("EXIT\n");
|
|
|
|
done_irq:
|
|
spin_unlock(&host->lock);
|
|
return IRQ_RETVAL(handled);
|
|
}
|
|
|
|
static inline void pdc_packet_start(struct ata_queued_cmd *qc)
|
|
{
|
|
struct ata_port *ap = qc->ap;
|
|
struct pdc_port_priv *pp = ap->private_data;
|
|
void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
|
|
unsigned int port_no = ap->port_no;
|
|
u8 seq = (u8) (port_no + 1);
|
|
|
|
VPRINTK("ENTER, ap %p\n", ap);
|
|
|
|
writel(0x00000001, mmio + (seq * 4));
|
|
readl(mmio + (seq * 4)); /* flush */
|
|
|
|
pp->pkt[2] = seq;
|
|
wmb(); /* flush PRD, pkt writes */
|
|
writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
|
|
readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
|
|
}
|
|
|
|
static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
|
|
{
|
|
switch (qc->tf.protocol) {
|
|
case ATA_PROT_ATAPI_NODATA:
|
|
if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
|
|
break;
|
|
/*FALLTHROUGH*/
|
|
case ATA_PROT_ATAPI_DMA:
|
|
case ATA_PROT_DMA:
|
|
case ATA_PROT_NODATA:
|
|
pdc_packet_start(qc);
|
|
return 0;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ata_qc_issue_prot(qc);
|
|
}
|
|
|
|
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
|
{
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
ata_tf_load(ap, tf);
|
|
}
|
|
|
|
|
|
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
|
{
|
|
WARN_ON (tf->protocol == ATA_PROT_DMA ||
|
|
tf->protocol == ATA_PROT_NODATA);
|
|
ata_exec_command(ap, tf);
|
|
}
|
|
|
|
static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
|
|
{
|
|
u8 *scsicmd = qc->scsicmd->cmnd;
|
|
int pio = 1; /* atapi dma off by default */
|
|
|
|
/* Whitelist commands that may use DMA. */
|
|
switch (scsicmd[0]) {
|
|
case WRITE_12:
|
|
case WRITE_10:
|
|
case WRITE_6:
|
|
case READ_12:
|
|
case READ_10:
|
|
case READ_6:
|
|
case 0xad: /* READ_DVD_STRUCTURE */
|
|
case 0xbe: /* READ_CD */
|
|
pio = 0;
|
|
}
|
|
/* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
|
|
if (scsicmd[0] == WRITE_10) {
|
|
unsigned int lba;
|
|
lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
|
|
if (lba >= 0xFFFF4FA2)
|
|
pio = 1;
|
|
}
|
|
return pio;
|
|
}
|
|
|
|
static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
|
|
{
|
|
/* First generation chips cannot use ATAPI DMA on SATA ports */
|
|
return 1;
|
|
}
|
|
|
|
static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base,
|
|
void __iomem *scr_addr)
|
|
{
|
|
port->cmd_addr = base;
|
|
port->data_addr = base;
|
|
port->feature_addr =
|
|
port->error_addr = base + 0x4;
|
|
port->nsect_addr = base + 0x8;
|
|
port->lbal_addr = base + 0xc;
|
|
port->lbam_addr = base + 0x10;
|
|
port->lbah_addr = base + 0x14;
|
|
port->device_addr = base + 0x18;
|
|
port->command_addr =
|
|
port->status_addr = base + 0x1c;
|
|
port->altstatus_addr =
|
|
port->ctl_addr = base + 0x38;
|
|
port->scr_addr = scr_addr;
|
|
}
|
|
|
|
|
|
static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
|
|
{
|
|
void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
|
|
struct pdc_host_priv *hp = pe->private_data;
|
|
int hotplug_offset;
|
|
u32 tmp;
|
|
|
|
if (hp->flags & PDC_FLAG_GEN_II)
|
|
hotplug_offset = PDC2_SATA_PLUG_CSR;
|
|
else
|
|
hotplug_offset = PDC_SATA_PLUG_CSR;
|
|
|
|
/*
|
|
* Except for the hotplug stuff, this is voodoo from the
|
|
* Promise driver. Label this entire section
|
|
* "TODO: figure out why we do this"
|
|
*/
|
|
|
|
/* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
|
|
tmp = readl(mmio + PDC_FLASH_CTL);
|
|
tmp |= 0x02000; /* bit 13 (enable bmr burst) */
|
|
if (!(hp->flags & PDC_FLAG_GEN_II))
|
|
tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
|
|
writel(tmp, mmio + PDC_FLASH_CTL);
|
|
|
|
/* clear plug/unplug flags for all ports */
|
|
tmp = readl(mmio + hotplug_offset);
|
|
writel(tmp | 0xff, mmio + hotplug_offset);
|
|
|
|
/* mask plug/unplug ints */
|
|
tmp = readl(mmio + hotplug_offset);
|
|
writel(tmp | 0xff0000, mmio + hotplug_offset);
|
|
|
|
/* don't initialise TBG or SLEW on 2nd generation chips */
|
|
if (hp->flags & PDC_FLAG_GEN_II)
|
|
return;
|
|
|
|
/* reduce TBG clock to 133 Mhz. */
|
|
tmp = readl(mmio + PDC_TBG_MODE);
|
|
tmp &= ~0x30000; /* clear bit 17, 16*/
|
|
tmp |= 0x10000; /* set bit 17:16 = 0:1 */
|
|
writel(tmp, mmio + PDC_TBG_MODE);
|
|
|
|
readl(mmio + PDC_TBG_MODE); /* flush */
|
|
msleep(10);
|
|
|
|
/* adjust slew rate control register. */
|
|
tmp = readl(mmio + PDC_SLEW_CTL);
|
|
tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
|
|
tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
|
|
writel(tmp, mmio + PDC_SLEW_CTL);
|
|
}
|
|
|
|
static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
static int printed_version;
|
|
struct ata_probe_ent *probe_ent;
|
|
struct pdc_host_priv *hp;
|
|
void __iomem *base;
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
|
int rc;
|
|
u8 tmp;
|
|
|
|
if (!printed_version++)
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
|
|
|
rc = pcim_enable_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
|
|
if (rc == -EBUSY)
|
|
pcim_pin_device(pdev);
|
|
if (rc)
|
|
return rc;
|
|
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
return rc;
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
if (rc)
|
|
return rc;
|
|
|
|
probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
|
|
if (probe_ent == NULL)
|
|
return -ENOMEM;
|
|
|
|
probe_ent->dev = pci_dev_to_dev(pdev);
|
|
INIT_LIST_HEAD(&probe_ent->node);
|
|
|
|
hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
|
|
if (hp == NULL)
|
|
return -ENOMEM;
|
|
|
|
probe_ent->private_data = hp;
|
|
|
|
probe_ent->sht = pdc_port_info[board_idx].sht;
|
|
probe_ent->port_flags = pdc_port_info[board_idx].flags;
|
|
probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
|
|
probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
|
|
probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
|
|
probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
|
|
|
|
probe_ent->irq = pdev->irq;
|
|
probe_ent->irq_flags = IRQF_SHARED;
|
|
probe_ent->iomap = pcim_iomap_table(pdev);
|
|
|
|
base = probe_ent->iomap[PDC_MMIO_BAR];
|
|
|
|
pdc_ata_setup_port(&probe_ent->port[0], base + 0x200, base + 0x400);
|
|
pdc_ata_setup_port(&probe_ent->port[1], base + 0x280, base + 0x500);
|
|
|
|
/* notice 4-port boards */
|
|
switch (board_idx) {
|
|
case board_40518:
|
|
hp->flags |= PDC_FLAG_GEN_II;
|
|
/* Fall through */
|
|
case board_20319:
|
|
probe_ent->n_ports = 4;
|
|
pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, base + 0x600);
|
|
pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, base + 0x700);
|
|
break;
|
|
case board_2057x:
|
|
hp->flags |= PDC_FLAG_GEN_II;
|
|
/* Fall through */
|
|
case board_2037x:
|
|
/* TX2plus boards also have a PATA port */
|
|
tmp = readb(base + PDC_FLASH_CTL+1);
|
|
if (!(tmp & 0x80)) {
|
|
probe_ent->n_ports = 3;
|
|
pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
|
|
hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
|
|
printk(KERN_INFO DRV_NAME " PATA port found\n");
|
|
} else
|
|
probe_ent->n_ports = 2;
|
|
hp->port_flags[0] = ATA_FLAG_SATA;
|
|
hp->port_flags[1] = ATA_FLAG_SATA;
|
|
break;
|
|
case board_20619:
|
|
probe_ent->n_ports = 4;
|
|
pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
|
|
pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, NULL);
|
|
break;
|
|
default:
|
|
BUG();
|
|
break;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
/* initialize adapter */
|
|
pdc_host_init(board_idx, probe_ent);
|
|
|
|
if (!ata_device_add(probe_ent))
|
|
return -ENODEV;
|
|
|
|
devm_kfree(&pdev->dev, probe_ent);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int __init pdc_ata_init(void)
|
|
{
|
|
return pci_register_driver(&pdc_ata_pci_driver);
|
|
}
|
|
|
|
|
|
static void __exit pdc_ata_exit(void)
|
|
{
|
|
pci_unregister_driver(&pdc_ata_pci_driver);
|
|
}
|
|
|
|
|
|
MODULE_AUTHOR("Jeff Garzik");
|
|
MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_init(pdc_ata_init);
|
|
module_exit(pdc_ata_exit);
|