![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
1211 lines
30 KiB
C
1211 lines
30 KiB
C
/*
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* linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver
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*
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* Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
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*
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* Copyright (C) 2006 Malcolm Noyes
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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This is the AT91 MCI driver that has been tested with both MMC cards
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and SD-cards. Boards that support write protect are now supported.
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The CCAT91SBC001 board does not support SD cards.
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The three entry points are at91_mci_request, at91_mci_set_ios
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and at91_mci_get_ro.
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SET IOS
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This configures the device to put it into the correct mode and clock speed
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required.
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MCI REQUEST
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MCI request processes the commands sent in the mmc_request structure. This
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can consist of a processing command and a stop command in the case of
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multiple block transfers.
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There are three main types of request, commands, reads and writes.
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Commands are straight forward. The command is submitted to the controller and
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the request function returns. When the controller generates an interrupt to indicate
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the command is finished, the response to the command are read and the mmc_request_done
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function called to end the request.
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Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
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controller to manage the transfers.
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A read is done from the controller directly to the scatterlist passed in from the request.
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Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
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swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug.
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The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
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A write is slightly different in that the bytes to write are read from the scatterlist
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into a dma memory buffer (this is in case the source buffer should be read only). The
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entire write buffer is then done from this single dma memory buffer.
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The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
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GET RO
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Gets the status of the write protect pin, if available.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <linux/atmel_pdc.h>
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#include <linux/gfp.h>
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#include <linux/mmc/host.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/gpio.h>
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#include <mach/board.h>
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#include <mach/cpu.h>
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#include <mach/at91_mci.h>
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#define DRIVER_NAME "at91_mci"
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static inline int at91mci_is_mci1rev2xx(void)
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{
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return ( cpu_is_at91sam9260()
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|| cpu_is_at91sam9263()
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|| cpu_is_at91cap9()
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|| cpu_is_at91sam9rl()
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|| cpu_is_at91sam9g10()
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|| cpu_is_at91sam9g20()
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);
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}
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#define FL_SENT_COMMAND (1 << 0)
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#define FL_SENT_STOP (1 << 1)
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#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
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| AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
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| AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
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#define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
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#define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
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#define MCI_BLKSIZE 512
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#define MCI_MAXBLKSIZE 4095
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#define MCI_BLKATONCE 256
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#define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE)
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/*
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* Low level type for this driver
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*/
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struct at91mci_host
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{
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struct mmc_host *mmc;
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struct mmc_command *cmd;
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struct mmc_request *request;
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void __iomem *baseaddr;
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int irq;
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struct at91_mmc_data *board;
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int present;
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struct clk *mci_clk;
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/*
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* Flag indicating when the command has been sent. This is used to
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* work out whether or not to send the stop
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*/
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unsigned int flags;
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/* flag for current bus settings */
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u32 bus_mode;
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/* DMA buffer used for transmitting */
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unsigned int* buffer;
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dma_addr_t physical_address;
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unsigned int total_length;
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/* Latest in the scatterlist that has been enabled for transfer, but not freed */
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int in_use_index;
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/* Latest in the scatterlist that has been enabled for transfer */
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int transfer_index;
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/* Timer for timeouts */
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struct timer_list timer;
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};
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/*
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* Reset the controller and restore most of the state
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*/
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static void at91_reset_host(struct at91mci_host *host)
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{
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unsigned long flags;
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u32 mr;
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u32 sdcr;
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u32 dtor;
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u32 imr;
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local_irq_save(flags);
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imr = at91_mci_read(host, AT91_MCI_IMR);
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at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
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/* save current state */
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mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
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sdcr = at91_mci_read(host, AT91_MCI_SDCR);
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dtor = at91_mci_read(host, AT91_MCI_DTOR);
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/* reset the controller */
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at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
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/* restore state */
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at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
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at91_mci_write(host, AT91_MCI_MR, mr);
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at91_mci_write(host, AT91_MCI_SDCR, sdcr);
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at91_mci_write(host, AT91_MCI_DTOR, dtor);
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at91_mci_write(host, AT91_MCI_IER, imr);
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/* make sure sdio interrupts will fire */
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at91_mci_read(host, AT91_MCI_SR);
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local_irq_restore(flags);
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}
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static void at91_timeout_timer(unsigned long data)
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{
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struct at91mci_host *host;
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host = (struct at91mci_host *)data;
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if (host->request) {
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dev_err(host->mmc->parent, "Timeout waiting end of packet\n");
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if (host->cmd && host->cmd->data) {
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host->cmd->data->error = -ETIMEDOUT;
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} else {
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if (host->cmd)
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host->cmd->error = -ETIMEDOUT;
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else
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host->request->cmd->error = -ETIMEDOUT;
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}
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at91_reset_host(host);
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mmc_request_done(host->mmc, host->request);
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}
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}
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/*
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* Copy from sg to a dma block - used for transfers
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*/
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static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
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{
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unsigned int len, i, size;
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unsigned *dmabuf = host->buffer;
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size = data->blksz * data->blocks;
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len = data->sg_len;
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/* MCI1 rev2xx Data Write Operation and number of bytes erratum */
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if (at91mci_is_mci1rev2xx())
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if (host->total_length == 12)
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memset(dmabuf, 0, 12);
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/*
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* Just loop through all entries. Size might not
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* be the entire list though so make sure that
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* we do not transfer too much.
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*/
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for (i = 0; i < len; i++) {
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struct scatterlist *sg;
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int amount;
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unsigned int *sgbuffer;
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sg = &data->sg[i];
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sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
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amount = min(size, sg->length);
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size -= amount;
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if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
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int index;
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for (index = 0; index < (amount / 4); index++)
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*dmabuf++ = swab32(sgbuffer[index]);
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} else {
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char *tmpv = (char *)dmabuf;
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memcpy(tmpv, sgbuffer, amount);
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tmpv += amount;
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dmabuf = (unsigned *)tmpv;
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}
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kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
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if (size == 0)
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break;
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}
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/*
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* Check that we didn't get a request to transfer
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* more data than can fit into the SG list.
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*/
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BUG_ON(size != 0);
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}
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/*
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* Handle after a dma read
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*/
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static void at91_mci_post_dma_read(struct at91mci_host *host)
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{
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struct mmc_command *cmd;
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struct mmc_data *data;
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unsigned int len, i, size;
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unsigned *dmabuf = host->buffer;
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pr_debug("post dma read\n");
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cmd = host->cmd;
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if (!cmd) {
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pr_debug("no command\n");
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return;
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}
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data = cmd->data;
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if (!data) {
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pr_debug("no data\n");
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return;
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}
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size = data->blksz * data->blocks;
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len = data->sg_len;
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at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
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at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
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for (i = 0; i < len; i++) {
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struct scatterlist *sg;
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int amount;
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unsigned int *sgbuffer;
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sg = &data->sg[i];
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sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
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amount = min(size, sg->length);
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size -= amount;
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if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
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int index;
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for (index = 0; index < (amount / 4); index++)
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sgbuffer[index] = swab32(*dmabuf++);
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} else {
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char *tmpv = (char *)dmabuf;
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memcpy(sgbuffer, tmpv, amount);
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tmpv += amount;
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dmabuf = (unsigned *)tmpv;
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}
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kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
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dmac_flush_range((void *)sgbuffer, ((void *)sgbuffer) + amount);
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data->bytes_xfered += amount;
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if (size == 0)
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break;
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}
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pr_debug("post dma read done\n");
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}
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/*
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* Handle transmitted data
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*/
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static void at91_mci_handle_transmitted(struct at91mci_host *host)
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{
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struct mmc_command *cmd;
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struct mmc_data *data;
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pr_debug("Handling the transmit\n");
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/* Disable the transfer */
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at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
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/* Now wait for cmd ready */
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at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
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cmd = host->cmd;
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if (!cmd) return;
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data = cmd->data;
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if (!data) return;
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if (cmd->data->blocks > 1) {
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pr_debug("multiple write : wait for BLKE...\n");
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at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
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} else
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at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
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}
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/*
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* Update bytes tranfered count during a write operation
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*/
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static void at91_mci_update_bytes_xfered(struct at91mci_host *host)
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{
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struct mmc_data *data;
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/* always deal with the effective request (and not the current cmd) */
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if (host->request->cmd && host->request->cmd->error != 0)
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return;
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if (host->request->data) {
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data = host->request->data;
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if (data->flags & MMC_DATA_WRITE) {
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/* card is in IDLE mode now */
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pr_debug("-> bytes_xfered %d, total_length = %d\n",
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data->bytes_xfered, host->total_length);
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data->bytes_xfered = data->blksz * data->blocks;
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}
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}
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}
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/*Handle after command sent ready*/
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static int at91_mci_handle_cmdrdy(struct at91mci_host *host)
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{
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if (!host->cmd)
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return 1;
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else if (!host->cmd->data) {
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if (host->flags & FL_SENT_STOP) {
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/*After multi block write, we must wait for NOTBUSY*/
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at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
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} else return 1;
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} else if (host->cmd->data->flags & MMC_DATA_WRITE) {
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/*After sendding multi-block-write command, start DMA transfer*/
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at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
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at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
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}
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/* command not completed, have to wait */
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return 0;
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}
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/*
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* Enable the controller
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*/
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static void at91_mci_enable(struct at91mci_host *host)
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{
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unsigned int mr;
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at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
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at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
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at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
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mr = AT91_MCI_PDCMODE | 0x34a;
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if (at91mci_is_mci1rev2xx())
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mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
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at91_mci_write(host, AT91_MCI_MR, mr);
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/* use Slot A or B (only one at same time) */
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at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
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}
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/*
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* Disable the controller
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*/
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static void at91_mci_disable(struct at91mci_host *host)
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{
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at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
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}
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/*
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* Send a command
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*/
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static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
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{
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unsigned int cmdr, mr;
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unsigned int block_length;
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struct mmc_data *data = cmd->data;
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unsigned int blocks;
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unsigned int ier = 0;
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host->cmd = cmd;
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/* Needed for leaving busy state before CMD1 */
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if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
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pr_debug("Clearing timeout\n");
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at91_mci_write(host, AT91_MCI_ARGR, 0);
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at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
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while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
|
|
/* spin */
|
|
pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
|
|
}
|
|
}
|
|
|
|
cmdr = cmd->opcode;
|
|
|
|
if (mmc_resp_type(cmd) == MMC_RSP_NONE)
|
|
cmdr |= AT91_MCI_RSPTYP_NONE;
|
|
else {
|
|
/* if a response is expected then allow maximum response latancy */
|
|
cmdr |= AT91_MCI_MAXLAT;
|
|
/* set 136 bit response for R2, 48 bit response otherwise */
|
|
if (mmc_resp_type(cmd) == MMC_RSP_R2)
|
|
cmdr |= AT91_MCI_RSPTYP_136;
|
|
else
|
|
cmdr |= AT91_MCI_RSPTYP_48;
|
|
}
|
|
|
|
if (data) {
|
|
|
|
if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) {
|
|
if (data->blksz & 0x3) {
|
|
pr_debug("Unsupported block size\n");
|
|
cmd->error = -EINVAL;
|
|
mmc_request_done(host->mmc, host->request);
|
|
return;
|
|
}
|
|
if (data->flags & MMC_DATA_STREAM) {
|
|
pr_debug("Stream commands not supported\n");
|
|
cmd->error = -EINVAL;
|
|
mmc_request_done(host->mmc, host->request);
|
|
return;
|
|
}
|
|
}
|
|
|
|
block_length = data->blksz;
|
|
blocks = data->blocks;
|
|
|
|
/* always set data start - also set direction flag for read */
|
|
if (data->flags & MMC_DATA_READ)
|
|
cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
|
|
else if (data->flags & MMC_DATA_WRITE)
|
|
cmdr |= AT91_MCI_TRCMD_START;
|
|
|
|
if (data->flags & MMC_DATA_STREAM)
|
|
cmdr |= AT91_MCI_TRTYP_STREAM;
|
|
if (data->blocks > 1)
|
|
cmdr |= AT91_MCI_TRTYP_MULTIPLE;
|
|
}
|
|
else {
|
|
block_length = 0;
|
|
blocks = 0;
|
|
}
|
|
|
|
if (host->flags & FL_SENT_STOP)
|
|
cmdr |= AT91_MCI_TRCMD_STOP;
|
|
|
|
if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
|
|
cmdr |= AT91_MCI_OPDCMD;
|
|
|
|
/*
|
|
* Set the arguments and send the command
|
|
*/
|
|
pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
|
|
cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
|
|
|
|
if (!data) {
|
|
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS);
|
|
at91_mci_write(host, ATMEL_PDC_RPR, 0);
|
|
at91_mci_write(host, ATMEL_PDC_RCR, 0);
|
|
at91_mci_write(host, ATMEL_PDC_RNPR, 0);
|
|
at91_mci_write(host, ATMEL_PDC_RNCR, 0);
|
|
at91_mci_write(host, ATMEL_PDC_TPR, 0);
|
|
at91_mci_write(host, ATMEL_PDC_TCR, 0);
|
|
at91_mci_write(host, ATMEL_PDC_TNPR, 0);
|
|
at91_mci_write(host, ATMEL_PDC_TNCR, 0);
|
|
ier = AT91_MCI_CMDRDY;
|
|
} else {
|
|
/* zero block length and PDC mode */
|
|
mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff;
|
|
mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0;
|
|
mr |= (block_length << 16);
|
|
mr |= AT91_MCI_PDCMODE;
|
|
at91_mci_write(host, AT91_MCI_MR, mr);
|
|
|
|
if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261()))
|
|
at91_mci_write(host, AT91_MCI_BLKR,
|
|
AT91_MCI_BLKR_BCNT(blocks) |
|
|
AT91_MCI_BLKR_BLKLEN(block_length));
|
|
|
|
/*
|
|
* Disable the PDC controller
|
|
*/
|
|
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
|
|
|
|
if (cmdr & AT91_MCI_TRCMD_START) {
|
|
data->bytes_xfered = 0;
|
|
host->transfer_index = 0;
|
|
host->in_use_index = 0;
|
|
if (cmdr & AT91_MCI_TRDIR) {
|
|
/*
|
|
* Handle a read
|
|
*/
|
|
host->total_length = 0;
|
|
|
|
at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address);
|
|
at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ?
|
|
(blocks * block_length) : (blocks * block_length) / 4);
|
|
at91_mci_write(host, ATMEL_PDC_RNPR, 0);
|
|
at91_mci_write(host, ATMEL_PDC_RNCR, 0);
|
|
|
|
ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
|
|
}
|
|
else {
|
|
/*
|
|
* Handle a write
|
|
*/
|
|
host->total_length = block_length * blocks;
|
|
/*
|
|
* MCI1 rev2xx Data Write Operation and
|
|
* number of bytes erratum
|
|
*/
|
|
if (at91mci_is_mci1rev2xx())
|
|
if (host->total_length < 12)
|
|
host->total_length = 12;
|
|
|
|
at91_mci_sg_to_dma(host, data);
|
|
|
|
pr_debug("Transmitting %d bytes\n", host->total_length);
|
|
|
|
at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
|
|
at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ?
|
|
host->total_length : host->total_length / 4);
|
|
|
|
ier = AT91_MCI_CMDRDY;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Send the command and then enable the PDC - not the other way round as
|
|
* the data sheet says
|
|
*/
|
|
|
|
at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
|
|
at91_mci_write(host, AT91_MCI_CMDR, cmdr);
|
|
|
|
if (cmdr & AT91_MCI_TRCMD_START) {
|
|
if (cmdr & AT91_MCI_TRDIR)
|
|
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
|
|
}
|
|
|
|
/* Enable selected interrupts */
|
|
at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
|
|
}
|
|
|
|
/*
|
|
* Process the next step in the request
|
|
*/
|
|
static void at91_mci_process_next(struct at91mci_host *host)
|
|
{
|
|
if (!(host->flags & FL_SENT_COMMAND)) {
|
|
host->flags |= FL_SENT_COMMAND;
|
|
at91_mci_send_command(host, host->request->cmd);
|
|
}
|
|
else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
|
|
host->flags |= FL_SENT_STOP;
|
|
at91_mci_send_command(host, host->request->stop);
|
|
} else {
|
|
del_timer(&host->timer);
|
|
/* the at91rm9200 mci controller hangs after some transfers,
|
|
* and the workaround is to reset it after each transfer.
|
|
*/
|
|
if (cpu_is_at91rm9200())
|
|
at91_reset_host(host);
|
|
mmc_request_done(host->mmc, host->request);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Handle a command that has been completed
|
|
*/
|
|
static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status)
|
|
{
|
|
struct mmc_command *cmd = host->cmd;
|
|
struct mmc_data *data = cmd->data;
|
|
|
|
at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
|
|
|
|
cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
|
|
cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
|
|
cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
|
|
cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
|
|
|
|
pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n",
|
|
status, at91_mci_read(host, AT91_MCI_SR),
|
|
cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
|
|
|
|
if (status & AT91_MCI_ERRORS) {
|
|
if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) {
|
|
cmd->error = 0;
|
|
}
|
|
else {
|
|
if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) {
|
|
if (data) {
|
|
if (status & AT91_MCI_DTOE)
|
|
data->error = -ETIMEDOUT;
|
|
else if (status & AT91_MCI_DCRCE)
|
|
data->error = -EILSEQ;
|
|
}
|
|
} else {
|
|
if (status & AT91_MCI_RTOE)
|
|
cmd->error = -ETIMEDOUT;
|
|
else if (status & AT91_MCI_RCRCE)
|
|
cmd->error = -EILSEQ;
|
|
else
|
|
cmd->error = -EIO;
|
|
}
|
|
|
|
pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n",
|
|
cmd->error, data ? data->error : 0,
|
|
cmd->opcode, cmd->retries);
|
|
}
|
|
}
|
|
else
|
|
cmd->error = 0;
|
|
|
|
at91_mci_process_next(host);
|
|
}
|
|
|
|
/*
|
|
* Handle an MMC request
|
|
*/
|
|
static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
{
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
host->request = mrq;
|
|
host->flags = 0;
|
|
|
|
/* more than 1s timeout needed with slow SD cards */
|
|
mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
|
|
|
|
at91_mci_process_next(host);
|
|
}
|
|
|
|
/*
|
|
* Set the IOS
|
|
*/
|
|
static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
int clkdiv;
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
|
|
|
|
host->bus_mode = ios->bus_mode;
|
|
|
|
if (ios->clock == 0) {
|
|
/* Disable the MCI controller */
|
|
at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
|
|
clkdiv = 0;
|
|
}
|
|
else {
|
|
/* Enable the MCI controller */
|
|
at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
|
|
|
|
if ((at91_master_clock % (ios->clock * 2)) == 0)
|
|
clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
|
|
else
|
|
clkdiv = (at91_master_clock / ios->clock) / 2;
|
|
|
|
pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
|
|
at91_master_clock / (2 * (clkdiv + 1)));
|
|
}
|
|
if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
|
|
pr_debug("MMC: Setting controller bus width to 4\n");
|
|
at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
|
|
}
|
|
else {
|
|
pr_debug("MMC: Setting controller bus width to 1\n");
|
|
at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
|
|
}
|
|
|
|
/* Set the clock divider */
|
|
at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
|
|
|
|
/* maybe switch power to the card */
|
|
if (host->board->vcc_pin) {
|
|
switch (ios->power_mode) {
|
|
case MMC_POWER_OFF:
|
|
gpio_set_value(host->board->vcc_pin, 0);
|
|
break;
|
|
case MMC_POWER_UP:
|
|
gpio_set_value(host->board->vcc_pin, 1);
|
|
break;
|
|
case MMC_POWER_ON:
|
|
break;
|
|
default:
|
|
WARN_ON(1);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Handle an interrupt
|
|
*/
|
|
static irqreturn_t at91_mci_irq(int irq, void *devid)
|
|
{
|
|
struct at91mci_host *host = devid;
|
|
int completed = 0;
|
|
unsigned int int_status, int_mask;
|
|
|
|
int_status = at91_mci_read(host, AT91_MCI_SR);
|
|
int_mask = at91_mci_read(host, AT91_MCI_IMR);
|
|
|
|
pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
|
|
int_status & int_mask);
|
|
|
|
int_status = int_status & int_mask;
|
|
|
|
if (int_status & AT91_MCI_ERRORS) {
|
|
completed = 1;
|
|
|
|
if (int_status & AT91_MCI_UNRE)
|
|
pr_debug("MMC: Underrun error\n");
|
|
if (int_status & AT91_MCI_OVRE)
|
|
pr_debug("MMC: Overrun error\n");
|
|
if (int_status & AT91_MCI_DTOE)
|
|
pr_debug("MMC: Data timeout\n");
|
|
if (int_status & AT91_MCI_DCRCE)
|
|
pr_debug("MMC: CRC error in data\n");
|
|
if (int_status & AT91_MCI_RTOE)
|
|
pr_debug("MMC: Response timeout\n");
|
|
if (int_status & AT91_MCI_RENDE)
|
|
pr_debug("MMC: Response end bit error\n");
|
|
if (int_status & AT91_MCI_RCRCE)
|
|
pr_debug("MMC: Response CRC error\n");
|
|
if (int_status & AT91_MCI_RDIRE)
|
|
pr_debug("MMC: Response direction error\n");
|
|
if (int_status & AT91_MCI_RINDE)
|
|
pr_debug("MMC: Response index error\n");
|
|
} else {
|
|
/* Only continue processing if no errors */
|
|
|
|
if (int_status & AT91_MCI_TXBUFE) {
|
|
pr_debug("TX buffer empty\n");
|
|
at91_mci_handle_transmitted(host);
|
|
}
|
|
|
|
if (int_status & AT91_MCI_ENDRX) {
|
|
pr_debug("ENDRX\n");
|
|
at91_mci_post_dma_read(host);
|
|
}
|
|
|
|
if (int_status & AT91_MCI_RXBUFF) {
|
|
pr_debug("RX buffer full\n");
|
|
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
|
|
at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
|
|
completed = 1;
|
|
}
|
|
|
|
if (int_status & AT91_MCI_ENDTX)
|
|
pr_debug("Transmit has ended\n");
|
|
|
|
if (int_status & AT91_MCI_NOTBUSY) {
|
|
pr_debug("Card is ready\n");
|
|
at91_mci_update_bytes_xfered(host);
|
|
completed = 1;
|
|
}
|
|
|
|
if (int_status & AT91_MCI_DTIP)
|
|
pr_debug("Data transfer in progress\n");
|
|
|
|
if (int_status & AT91_MCI_BLKE) {
|
|
pr_debug("Block transfer has ended\n");
|
|
if (host->request->data && host->request->data->blocks > 1) {
|
|
/* multi block write : complete multi write
|
|
* command and send stop */
|
|
completed = 1;
|
|
} else {
|
|
at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
|
|
}
|
|
}
|
|
|
|
if (int_status & AT91_MCI_SDIOIRQA)
|
|
mmc_signal_sdio_irq(host->mmc);
|
|
|
|
if (int_status & AT91_MCI_SDIOIRQB)
|
|
mmc_signal_sdio_irq(host->mmc);
|
|
|
|
if (int_status & AT91_MCI_TXRDY)
|
|
pr_debug("Ready to transmit\n");
|
|
|
|
if (int_status & AT91_MCI_RXRDY)
|
|
pr_debug("Ready to receive\n");
|
|
|
|
if (int_status & AT91_MCI_CMDRDY) {
|
|
pr_debug("Command ready\n");
|
|
completed = at91_mci_handle_cmdrdy(host);
|
|
}
|
|
}
|
|
|
|
if (completed) {
|
|
pr_debug("Completed command\n");
|
|
at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
|
|
at91_mci_completed_command(host, int_status);
|
|
} else
|
|
at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
|
|
{
|
|
struct at91mci_host *host = _host;
|
|
int present = !gpio_get_value(irq_to_gpio(irq));
|
|
|
|
/*
|
|
* we expect this irq on both insert and remove,
|
|
* and use a short delay to debounce.
|
|
*/
|
|
if (present != host->present) {
|
|
host->present = present;
|
|
pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
|
|
present ? "insert" : "remove");
|
|
if (!present) {
|
|
pr_debug("****** Resetting SD-card bus width ******\n");
|
|
at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
|
|
}
|
|
/* 0.5s needed because of early card detect switch firing */
|
|
mmc_detect_change(host->mmc, msecs_to_jiffies(500));
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int at91_mci_get_ro(struct mmc_host *mmc)
|
|
{
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
|
|
if (host->board->wp_pin)
|
|
return !!gpio_get_value(host->board->wp_pin);
|
|
/*
|
|
* Board doesn't support read only detection; let the mmc core
|
|
* decide what to do.
|
|
*/
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
|
{
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
|
|
pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc),
|
|
host->board->slot_b ? 'B':'A', enable ? "enable" : "disable");
|
|
at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR,
|
|
host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA);
|
|
|
|
}
|
|
|
|
static const struct mmc_host_ops at91_mci_ops = {
|
|
.request = at91_mci_request,
|
|
.set_ios = at91_mci_set_ios,
|
|
.get_ro = at91_mci_get_ro,
|
|
.enable_sdio_irq = at91_mci_enable_sdio_irq,
|
|
};
|
|
|
|
/*
|
|
* Probe for the device
|
|
*/
|
|
static int __init at91_mci_probe(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc;
|
|
struct at91mci_host *host;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENXIO;
|
|
|
|
if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME))
|
|
return -EBUSY;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
|
|
if (!mmc) {
|
|
ret = -ENOMEM;
|
|
dev_dbg(&pdev->dev, "couldn't allocate mmc host\n");
|
|
goto fail6;
|
|
}
|
|
|
|
mmc->ops = &at91_mci_ops;
|
|
mmc->f_min = 375000;
|
|
mmc->f_max = 25000000;
|
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
mmc->caps = 0;
|
|
|
|
mmc->max_blk_size = MCI_MAXBLKSIZE;
|
|
mmc->max_blk_count = MCI_BLKATONCE;
|
|
mmc->max_req_size = MCI_BUFSIZE;
|
|
mmc->max_phys_segs = MCI_BLKATONCE;
|
|
mmc->max_hw_segs = MCI_BLKATONCE;
|
|
mmc->max_seg_size = MCI_BUFSIZE;
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
host->bus_mode = 0;
|
|
host->board = pdev->dev.platform_data;
|
|
if (host->board->wire4) {
|
|
if (at91mci_is_mci1rev2xx())
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
else
|
|
dev_warn(&pdev->dev, "4 wire bus mode not supported"
|
|
" - using 1 wire\n");
|
|
}
|
|
|
|
host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE,
|
|
&host->physical_address, GFP_KERNEL);
|
|
if (!host->buffer) {
|
|
ret = -ENOMEM;
|
|
dev_err(&pdev->dev, "Can't allocate transmit buffer\n");
|
|
goto fail5;
|
|
}
|
|
|
|
/* Add SDIO capability when available */
|
|
if (at91mci_is_mci1rev2xx()) {
|
|
/* at91mci MCI1 rev2xx sdio interrupt erratum */
|
|
if (host->board->wire4 || !host->board->slot_b)
|
|
mmc->caps |= MMC_CAP_SDIO_IRQ;
|
|
}
|
|
|
|
/*
|
|
* Reserve GPIOs ... board init code makes sure these pins are set
|
|
* up as GPIOs with the right direction (input, except for vcc)
|
|
*/
|
|
if (host->board->det_pin) {
|
|
ret = gpio_request(host->board->det_pin, "mmc_detect");
|
|
if (ret < 0) {
|
|
dev_dbg(&pdev->dev, "couldn't claim card detect pin\n");
|
|
goto fail4b;
|
|
}
|
|
}
|
|
if (host->board->wp_pin) {
|
|
ret = gpio_request(host->board->wp_pin, "mmc_wp");
|
|
if (ret < 0) {
|
|
dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n");
|
|
goto fail4;
|
|
}
|
|
}
|
|
if (host->board->vcc_pin) {
|
|
ret = gpio_request(host->board->vcc_pin, "mmc_vcc");
|
|
if (ret < 0) {
|
|
dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n");
|
|
goto fail3;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Get Clock
|
|
*/
|
|
host->mci_clk = clk_get(&pdev->dev, "mci_clk");
|
|
if (IS_ERR(host->mci_clk)) {
|
|
ret = -ENODEV;
|
|
dev_dbg(&pdev->dev, "no mci_clk?\n");
|
|
goto fail2;
|
|
}
|
|
|
|
/*
|
|
* Map I/O region
|
|
*/
|
|
host->baseaddr = ioremap(res->start, res->end - res->start + 1);
|
|
if (!host->baseaddr) {
|
|
ret = -ENOMEM;
|
|
goto fail1;
|
|
}
|
|
|
|
/*
|
|
* Reset hardware
|
|
*/
|
|
clk_enable(host->mci_clk); /* Enable the peripheral clock */
|
|
at91_mci_disable(host);
|
|
at91_mci_enable(host);
|
|
|
|
/*
|
|
* Allocate the MCI interrupt
|
|
*/
|
|
host->irq = platform_get_irq(pdev, 0);
|
|
ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED,
|
|
mmc_hostname(mmc), host);
|
|
if (ret) {
|
|
dev_dbg(&pdev->dev, "request MCI interrupt failed\n");
|
|
goto fail0;
|
|
}
|
|
|
|
setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host);
|
|
|
|
platform_set_drvdata(pdev, mmc);
|
|
|
|
/*
|
|
* Add host to MMC layer
|
|
*/
|
|
if (host->board->det_pin) {
|
|
host->present = !gpio_get_value(host->board->det_pin);
|
|
}
|
|
else
|
|
host->present = -1;
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
/*
|
|
* monitor card insertion/removal if we can
|
|
*/
|
|
if (host->board->det_pin) {
|
|
ret = request_irq(gpio_to_irq(host->board->det_pin),
|
|
at91_mmc_det_irq, 0, mmc_hostname(mmc), host);
|
|
if (ret)
|
|
dev_warn(&pdev->dev, "request MMC detect irq failed\n");
|
|
else
|
|
device_init_wakeup(&pdev->dev, 1);
|
|
}
|
|
|
|
pr_debug("Added MCI driver\n");
|
|
|
|
return 0;
|
|
|
|
fail0:
|
|
clk_disable(host->mci_clk);
|
|
iounmap(host->baseaddr);
|
|
fail1:
|
|
clk_put(host->mci_clk);
|
|
fail2:
|
|
if (host->board->vcc_pin)
|
|
gpio_free(host->board->vcc_pin);
|
|
fail3:
|
|
if (host->board->wp_pin)
|
|
gpio_free(host->board->wp_pin);
|
|
fail4:
|
|
if (host->board->det_pin)
|
|
gpio_free(host->board->det_pin);
|
|
fail4b:
|
|
if (host->buffer)
|
|
dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
|
|
host->buffer, host->physical_address);
|
|
fail5:
|
|
mmc_free_host(mmc);
|
|
fail6:
|
|
release_mem_region(res->start, res->end - res->start + 1);
|
|
dev_err(&pdev->dev, "probe failed, err %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Remove a device
|
|
*/
|
|
static int __exit at91_mci_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
struct at91mci_host *host;
|
|
struct resource *res;
|
|
|
|
if (!mmc)
|
|
return -1;
|
|
|
|
host = mmc_priv(mmc);
|
|
|
|
if (host->buffer)
|
|
dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
|
|
host->buffer, host->physical_address);
|
|
|
|
if (host->board->det_pin) {
|
|
if (device_can_wakeup(&pdev->dev))
|
|
free_irq(gpio_to_irq(host->board->det_pin), host);
|
|
device_init_wakeup(&pdev->dev, 0);
|
|
gpio_free(host->board->det_pin);
|
|
}
|
|
|
|
at91_mci_disable(host);
|
|
del_timer_sync(&host->timer);
|
|
mmc_remove_host(mmc);
|
|
free_irq(host->irq, host);
|
|
|
|
clk_disable(host->mci_clk); /* Disable the peripheral clock */
|
|
clk_put(host->mci_clk);
|
|
|
|
if (host->board->vcc_pin)
|
|
gpio_free(host->board->vcc_pin);
|
|
if (host->board->wp_pin)
|
|
gpio_free(host->board->wp_pin);
|
|
|
|
iounmap(host->baseaddr);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(res->start, res->end - res->start + 1);
|
|
|
|
mmc_free_host(mmc);
|
|
platform_set_drvdata(pdev, NULL);
|
|
pr_debug("MCI Removed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
int ret = 0;
|
|
|
|
if (host->board->det_pin && device_may_wakeup(&pdev->dev))
|
|
enable_irq_wake(host->board->det_pin);
|
|
|
|
if (mmc)
|
|
ret = mmc_suspend_host(mmc, state);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int at91_mci_resume(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
struct at91mci_host *host = mmc_priv(mmc);
|
|
int ret = 0;
|
|
|
|
if (host->board->det_pin && device_may_wakeup(&pdev->dev))
|
|
disable_irq_wake(host->board->det_pin);
|
|
|
|
if (mmc)
|
|
ret = mmc_resume_host(mmc);
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
#define at91_mci_suspend NULL
|
|
#define at91_mci_resume NULL
|
|
#endif
|
|
|
|
static struct platform_driver at91_mci_driver = {
|
|
.remove = __exit_p(at91_mci_remove),
|
|
.suspend = at91_mci_suspend,
|
|
.resume = at91_mci_resume,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init at91_mci_init(void)
|
|
{
|
|
return platform_driver_probe(&at91_mci_driver, at91_mci_probe);
|
|
}
|
|
|
|
static void __exit at91_mci_exit(void)
|
|
{
|
|
platform_driver_unregister(&at91_mci_driver);
|
|
}
|
|
|
|
module_init(at91_mci_init);
|
|
module_exit(at91_mci_exit);
|
|
|
|
MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
|
|
MODULE_AUTHOR("Nick Randell");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:at91_mci");
|