19e489aa9b
This series of changes adds the PRM reset driver nodes for am3/4, omap4/5 and dra7 SoCs. The reset driver changes make it easier to add support for various accelerators for TI SoCs in a more generic way. Note that this branch is based on the PRM reset driver changes branch. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl28UrgRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXPQvw/+Kz/OaUWXc6NCGqbgrjvQZbJMzWykeuP3 QyIzQ/k6x9B1VqkHvnmbAUKEpROXe7/t8QaVZs2WfQLb/3QvOJtEN5KlgGOC1ofF VLWR1aSU1bApDIbTf0tIhIEkmsm/qJvm4QlRBLahQEtP/2LRuZMybikBgbEteFMB zgMUPjqc//gGI1Y8H90ntWlCA0runosrxJ83qJ4O74RMzBiH30h3qZFq7Xt4O/az x0B4u+RBB3hnetq6oHBsk6TFbE0qmOBYSx81w40GM4Rn5Xgvq62PaoRHez/qLRRB 3GhtfIUb5bJX3w8wQF6wyIUQfIFjYKDut3mldx1zR01x8QwYMl5b8aD9M5MIern4 +KVT5rtjllnbMQYhOmQKky5UCKU1SOvYZDfN//4S68YF0DZ257vYFkeXIWHYA+pr Cc8lVAgCqDV5WlBBXy2F6uZC7vQCdpPFI2ljEPryiEumJ3FlK+nY7WmpusJ6grau BiJakyYS0dqqoJS+LH7GtB3PLChgGXIQd9SWF5NvCzbtr+4ve7dUCzTs/UitUpET 9B3kaoHE9s9UvozZkHFPxIhR7o2uAfSqUUMNCWplXy5jhPl6RFPB0myV66ai8v3U ZVO+EAF0Bx47zz0riBlqraiMBybohohZAijZjQztHyeKE2CfBc1ErUPFAur32bF6 ML9ze/G+SkI= =4DAS -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt PRM reset control dts changes for v5.5 merge window This series of changes adds the PRM reset driver nodes for am3/4, omap4/5 and dra7 SoCs. The reset driver changes make it easier to add support for various accelerators for TI SoCs in a more generic way. Note that this branch is based on the PRM reset driver changes branch. * tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap5: Add PRM data ARM: dts: am43xx: Add PRM data ARM: dts: am33xx: Add PRM data ARM: dts: omap4: add PRM nodes ARM: dts: dra7: add PRM nodes soc: ti: omap-prm: add omap5 PRM data soc: ti: omap-prm: add am4 PRM data soc: ti: omap-prm: add dra7 PRM data soc: ti: omap-prm: add data for am33xx soc: ti: omap-prm: add omap4 PRM data soc: ti: omap-prm: add support for denying idle for reset clockdomain soc: ti: omap-prm: poll for reset complete during de-assert soc: ti: add initial PRM driver with reset control support dt-bindings: omap: add new binding for PRM instances Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
403 lines
9.1 KiB
Plaintext
403 lines
9.1 KiB
Plaintext
/*
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* Device Tree Source for AM4372 SoC
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/am4.h>
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/ {
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compatible = "ti,am4372", "ti,am43";
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interrupt-parent = <&wakeupgen>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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memory@0 {
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device_type = "memory";
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reg = <0 0>;
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};
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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ethernet0 = &cpsw_emac0;
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ethernet1 = &cpsw_emac1;
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spi0 = &qspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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clock-latency = <300000>; /* From omap-cpufreq driver */
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};
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};
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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syscon = <&scm_conf>;
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opp50-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <950000 931000 969000>;
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opp-supported-hw = <0xFF 0x01>;
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opp-suspend;
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};
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opp100-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0xFF 0x04>;
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};
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opp120-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1200000 1176000 1224000>;
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opp-supported-hw = <0xFF 0x08>;
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};
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oppturbo-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1260000 1234800 1285200>;
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opp-supported-hw = <0xFF 0x10>;
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};
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oppnitro-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1325000 1298500 1351500>;
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opp-supported-hw = <0xFF 0x20>;
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};
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};
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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pm-sram = <&pm_sram_code
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&pm_sram_data>;
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};
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};
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gic: interrupt-controller@48241000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48241000 0x1000>,
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<0x48240100 0x0100>;
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@48281000 {
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compatible = "ti,omap4-wugen-mpu";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48281000 0x1000>;
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interrupt-parent = <&gic>;
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};
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scu: scu@48240000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x48240000 0x100>;
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};
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global_timer: timer@48240200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x48240200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&gic>;
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clocks = <&mpu_periphclk>;
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};
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local_timer: timer@48240600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x48240600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&gic>;
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clocks = <&mpu_periphclk>;
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};
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l2-cache-controller@48242000 {
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compatible = "arm,pl310-cache";
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reg = <0x48242000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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ocp@44000000 {
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compatible = "ti,am4372-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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ti,no-idle;
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reg = <0x44000000 0x400000
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0x44800000 0x400000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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l4_wkup: interconnect@44c00000 {
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wkup_m3: wkup_m3@100000 {
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compatible = "ti,am4372-wkup-m3";
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reg = <0x100000 0x4000>,
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<0x180000 0x2000>;
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reg-names = "umem", "dmem";
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ti,hwmods = "wkup_m3";
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ti,pm-firmware = "am335x-pm-firmware.elf";
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};
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};
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l4_per: interconnect@48000000 {
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};
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l4_fast: interconnect@4a000000 {
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};
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emif: emif@4c000000 {
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compatible = "ti,emif-am4372";
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reg = <0x4c000000 0x1000000>;
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ti,hwmods = "emif";
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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ti,no-idle;
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sram = <&pm_sram_code
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&pm_sram_data>;
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};
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edma: edma@49000000 {
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compatible = "ti,edma3-tpcc";
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ti,hwmods = "tpcc";
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reg = <0x49000000 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 0>;
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ti,edma-memcpy-channels = <58 59>;
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};
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edma_tptc0: tptc@49800000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc0";
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reg = <0x49800000 0x100000>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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edma_tptc1: tptc@49900000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc1";
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reg = <0x49900000 0x100000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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edma_tptc2: tptc@49a00000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc2";
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reg = <0x49a00000 0x100000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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target-module@47810000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x478102fc 0x4>,
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<0x47810110 0x4>,
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<0x47810114 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x47810000 0x1000>;
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mmc3: mmc@0 {
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compatible = "ti,omap4-hsmmc";
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ti,needs-special-reset;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x1000>;
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};
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};
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sham: sham@53100000 {
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compatible = "ti,omap5-sham";
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ti,hwmods = "sham";
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reg = <0x53100000 0x300>;
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dmas = <&edma 36 0>;
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dma-names = "rx";
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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};
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aes: aes@53501000 {
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compatible = "ti,omap4-aes";
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ti,hwmods = "aes";
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reg = <0x53501000 0xa0>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&edma 6 0>,
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<&edma 5 0>;
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dma-names = "tx", "rx";
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};
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des: des@53701000 {
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compatible = "ti,omap4-des";
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ti,hwmods = "des";
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reg = <0x53701000 0xa0>;
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interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&edma 34 0>,
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<&edma 33 0>;
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dma-names = "tx", "rx";
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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dmas = <&edma 52 0>;
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dma-names = "rxtx";
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clocks = <&l3s_gclk>;
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clock-names = "fck";
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reg = <0x50000000 0x2000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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gpmc,num-cs = <7>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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qspi: spi@47900000 {
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compatible = "ti,am4372-qspi";
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reg = <0x47900000 0x100>,
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<0x30000000 0x4000000>;
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reg-names = "qspi_base", "qspi_mmap";
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "qspi";
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interrupts = <0 138 0x4>;
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num-cs = <4>;
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status = "disabled";
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};
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dss: dss@4832a000 {
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compatible = "ti,omap3-dss";
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reg = <0x4832a000 0x200>;
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status = "disabled";
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ti,hwmods = "dss_core";
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clocks = <&disp_clk>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dispc: dispc@4832a400 {
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compatible = "ti,omap3-dispc";
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reg = <0x4832a400 0x400>;
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "dss_dispc";
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clocks = <&disp_clk>;
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clock-names = "fck";
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max-memory-bandwidth = <230000000>;
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};
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rfbi: rfbi@4832a800 {
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compatible = "ti,omap3-rfbi";
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reg = <0x4832a800 0x100>;
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ti,hwmods = "dss_rfbi";
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clocks = <&disp_clk>;
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clock-names = "fck";
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status = "disabled";
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};
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};
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ocmcram: sram@40300000 {
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compatible = "mmio-sram";
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reg = <0x40300000 0x40000>; /* 256k */
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ranges = <0x0 0x40300000 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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pm_sram_code: pm-code-sram@0 {
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compatible = "ti,sram";
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reg = <0x0 0x1000>;
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protect-exec;
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};
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pm_sram_data: pm-data-sram@1000 {
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compatible = "ti,sram";
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reg = <0x1000 0x1000>;
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pool;
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};
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};
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};
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};
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#include "am437x-l4.dtsi"
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#include "am43xx-clocks.dtsi"
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&prcm {
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prm_gfx: prm@400 {
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compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
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reg = <0x400 0x100>;
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#reset-cells = <1>;
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};
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prm_per: prm@800 {
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compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
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reg = <0x800 0x100>;
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#reset-cells = <1>;
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};
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prm_wkup: prm@2000 {
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compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
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reg = <0x2000 0x100>;
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#reset-cells = <1>;
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};
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prm_device: prm@4000 {
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compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
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reg = <0x4000 0x100>;
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#reset-cells = <1>;
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};
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};
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