0672d22a19
Commit 6d4cd041f0 ("net: phy: at803x: disable delay only for RGMII mode")
exposed an issue on imx DTS files using AR8031/AR8035 PHYs.
The end result is that the boards can no longer obtain an IP address
via UDHCP, for example.
Quoting Andrew Lunn:
"The problem here is, all the DTs were broken since day 0. However,
because the PHY driver was also broken, nobody noticed and it
worked. Now that the PHY driver has been fixed, all the bugs in the
DTs now become an issue"
To fix this problem, the phy-mode property needs to be "rgmii-id", which
has the following meaning as per
Documentation/devicetree/bindings/net/ethernet.txt:
"RGMII with internal RX and TX delays provided by the PHY, the MAC should
not add the RX or TX delays in this case)"
Tested on imx6-sabresd, imx6sx-sdb and imx7d-pico boards with
successfully restored networking.
Based on the initial submission from Steve Twiss for the
imx6qdl-sabresd.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Soeren Moch <smoch@web.de>
Tested-by: Steve Twiss <stwiss.opensource@diasemi.com>
Tested-by: Adam Thomson <Adam.Thomson@diasemi.com>
Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com>
Tested-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
586 lines
13 KiB
Plaintext
586 lines
13 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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//
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// Copyright 2017 NXP
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/dts-v1/;
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#include "imx7d.dtsi"
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/ {
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/* Will be filled by the bootloader */
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0>;
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};
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reg_wlreg_on: regulator-wlreg_on {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_wlreg_on>;
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regulator-name = "wlreg_on";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_2p5v: regulator-2p5v {
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compatible = "regulator-fixed";
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regulator-name = "2P5V";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_pwr>;
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
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};
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reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg2_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_vref_1v8: regulator-vref-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "vref-1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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usdhc2_pwrseq: usdhc2_pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
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clock-names = "ext_clock";
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};
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};
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&clks {
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assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
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<&clks IMX7D_CLKO2_ROOT_DIV>;
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assigned-clock-parents = <&clks IMX7D_CKIL>;
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assigned-clock-rates = <0>, <32768>;
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};
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&ecspi3 {
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cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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status = "okay";
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};
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can2>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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pmic: pfuze3000@8 {
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compatible = "fsl,pfuze3000";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1a {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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/* use sw1c_reg to align with pfuze100/pfuze200 */
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sw1c_reg: sw1b {
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1475000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1850000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a_reg: sw3 {
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1650000>;
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regulator-boot-on;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1_reg: vldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen2_reg: vldo2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen3_reg: vccsd {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: v33 {
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regulator-min-microvolt = <2850000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vldo3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vldo4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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};
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&sai1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
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<&clks IMX7D_SAI1_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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status = "okay";
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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status = "okay";
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>;
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status = "okay";
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};
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&pwm4 { /* Backlight */
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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status = "okay";
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};
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&uart6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart6>;
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assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart7 { /* Bluetooth */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart7>;
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assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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uart-has-rtscts;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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tuning-step = <2>;
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vmmc-supply = <®_3p3v>;
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wakeup-source;
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no-1-8-v;
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keep-power-in-suspend;
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status = "okay";
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};
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&usdhc2 { /* Wifi SDIO */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
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no-1-8-v;
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non-removable;
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keep-power-in-suspend;
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wakeup-source;
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vmmc-supply = <®_wlreg_on>;
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mmc-pwrseq = <&usdhc2_pwrseq>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
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assigned-clock-rates = <400000000>;
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bus-width = <8>;
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no-1-8-v;
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fsl,tuning-step = <2>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi3: ecspi3grp {
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fsl,pins = <
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MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
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MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
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MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
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MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
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MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f
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MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
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MX7D_PAD_SD2_WP__ENET1_MDC 0x3
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
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MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
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>;
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};
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pinctrl_can1: can1frp {
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fsl,pins = <
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MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
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MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
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>;
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};
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pinctrl_can2: can2frp {
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fsl,pins = <
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MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
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MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
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MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
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>;
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};
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pinctrl_pwm1: pwm1 {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
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>;
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};
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pinctrl_pwm2: pwm2 {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
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>;
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};
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pinctrl_pwm3: pwm3 {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
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>;
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};
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pinctrl_reg_wlreg_on: regregongrp {
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fsl,pins = <
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MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
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>;
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};
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pinctrl_sai1: sai1grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
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MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
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MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
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MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
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>;
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};
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
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MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart6: uart6grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
|
|
MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
|
|
MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79
|
|
MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart7: uart7grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79
|
|
MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79
|
|
MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79
|
|
MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg1_pwr: usbotg_pwr {
|
|
fsl,pins = <
|
|
MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
|
|
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
|
|
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
|
|
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
|
|
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
|
|
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
|
|
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
|
|
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
|
|
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
|
|
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
|
|
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
|
|
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
|
|
fsl,pins = <
|
|
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
|
|
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
|
|
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
|
|
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
|
|
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
|
|
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
|
|
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
|
|
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
|
|
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
|
|
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
|
|
>;
|
|
};
|
|
};
|
|
|
|
&iomuxc_lpsr {
|
|
pinctrl_wifi_clk: wificlkgrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
|
|
>;
|
|
};
|
|
};
|