1bfe610491
i.MX7ULP does NOT support runtime switching clock source for PCC,
APLL_PFD1 by default is usdhc's clock source, so just use it
in kernel to avoid below kernel dump during kernel boot up and
make sure kernel can boot up with SD root file-system.
[ 3.035892] Loading compiled-in X.509 certificates
[ 3.136301] sdhci-esdhc-imx 40370000.mmc: Got CD GPIO
[ 3.242886] mmc0: Reset 0x1 never completed.
[ 3.247190] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
[ 3.253751] mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00000002
[ 3.260218] mmc0: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
[ 3.266775] mmc0: sdhci: Argument: 0x00009a64 | Trn mode: 0x00000000
[ 3.273333] mmc0: sdhci: Present: 0x00088088 | Host ctl: 0x00000002
[ 3.279794] mmc0: sdhci: Power: 0x00000000 | Blk gap: 0x00000080
[ 3.286350] mmc0: sdhci: Wake-up: 0x00000008 | Clock: 0x0000007f
[ 3.292901] mmc0: sdhci: Timeout: 0x0000008c | Int stat: 0x00000000
[ 3.299364] mmc0: sdhci: Int enab: 0x007f010b | Sig enab: 0x00000000
[ 3.305918] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00008402
[ 3.312471] mmc0: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b400
[ 3.318934] mmc0: sdhci: Cmd: 0x0000113a | Max curr: 0x00ffffff
[ 3.325488] mmc0: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x0039b37f
[ 3.332040] mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x00400e00
[ 3.338501] mmc0: sdhci: Host ctl2: 0x00000000
[ 3.343051] mmc0: sdhci: ============================================
Fixes: 20434dc92c ("ARM: dts: imx: add common imx7ulp dtsi support")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
135 lines
2.7 KiB
Plaintext
135 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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/dts-v1/;
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#include "imx7ulp.dtsi"
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/ {
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model = "NXP i.MX7ULP EVK";
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compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
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chosen {
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stdout-path = &lpuart4;
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&tpm4 1 50000 0>;
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brightness-levels = <0 20 25 30 35 40 100>;
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default-brightness-level = <6>;
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status = "okay";
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};
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reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_vbus>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_vsd_3v3: regulator-vsd-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0_rst>;
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gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&lpuart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart4>;
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status = "okay";
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};
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&tpm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm0>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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over-current-active-low;
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status = "okay";
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};
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&usdhc0 {
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0>;
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cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_vsd_3v3>;
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status = "okay";
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};
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&iomuxc1 {
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
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>;
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bias-pull-up;
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};
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pinctrl_pwm0: pwm0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
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>;
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};
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pinctrl_usbotg1_vbus: otg1vbusgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC0__PTC0 0x20000
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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IMX7ULP_PAD_PTC16__USB1_OC2 0x10003
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
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>;
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};
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pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD0__PTD0 0x3
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>;
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};
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};
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