b7dbe349e1
With the driver installed, we can change the opp-v1 table format
to opp-v2.
In addition, move omap3 from whitelist to blacklist in cpufreq-dt-platdev
in the same patch, because doing either first breaks operation and
may make trouble in bisect.
We also can remove opp-v1 table for omap3-n950-n9 since its 1GHz
capability is now automatically detected.
We also fix a wrong OPP4 voltage for omap3430 which must be
0.6V + 54*12.5mV = 1275mV. Otherwise the twl4030 driver will reject
this OPP.
Note: the high speed OPPs that were not available in the opp-v1 tables
are tagged "turbo-mode;" which means they are not automatically
activated by the govenors or cpu-freq.
To enable you have to write
echo 1 >/sys/devices/system/cpu/cpufreq/boost
Note: to hard disable an OPP in a board.dts file use e.g.
&cpu0_opp_table: {
/delete-node/ opp1g-1000000000; /* do not use */
};
or alternatively:
&cpu0_opp_table: {
opp1g-1000000000 {
status = "disabled"; /* do not use */
};
};
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
198 lines
4.9 KiB
Plaintext
198 lines
4.9 KiB
Plaintext
/*
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* Device Tree Source for OMAP34xx/OMAP35xx SoC
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/media/omap3-isp.h>
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#include "omap3.dtsi"
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/ {
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cpus {
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cpu: cpu@0 {
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/* OMAP343x/OMAP35xx variants OPP1-6 */
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operating-points-v2 = <&cpu0_opp_table>;
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clock-latency = <300000>; /* From legacy driver */
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};
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};
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/* see Documentation/devicetree/bindings/opp/opp.txt */
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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syscon = <&scm_conf>;
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opp1-125000000 {
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opp-hz = /bits/ 64 <125000000>;
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/*
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* we currently only select the max voltage from table
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* Table 3-3 of the omap3530 Data sheet (SPRS507F).
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* Format is: <target min max>
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*/
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opp-microvolt = <975000 975000 975000>;
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/*
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* first value is silicon revision bit mask
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* second one 720MHz Device Identification bit mask
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*/
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opp-supported-hw = <0xffffffff 3>;
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};
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opp2-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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opp-microvolt = <1075000 1075000 1075000>;
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opp-supported-hw = <0xffffffff 3>;
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opp-suspend;
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};
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opp3-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <1200000 1200000 1200000>;
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opp-supported-hw = <0xffffffff 3>;
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};
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opp4-550000000 {
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opp-hz = /bits/ 64 <550000000>;
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opp-microvolt = <1275000 1275000 1275000>;
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opp-supported-hw = <0xffffffff 3>;
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};
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opp5-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1350000 1350000 1350000>;
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opp-supported-hw = <0xffffffff 3>;
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};
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opp6-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1350000 1350000 1350000>;
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/* only high-speed grade omap3530 devices */
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opp-supported-hw = <0xffffffff 2>;
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turbo-mode;
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};
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};
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ocp@68000000 {
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omap3_pmx_core2: pinmux@480025d8 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x480025d8 0x24>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <1>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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isp: isp@480bc000 {
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compatible = "ti,omap3-isp";
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reg = <0x480bc000 0x12fc
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0x480bd800 0x017c>;
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interrupts = <24>;
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iommus = <&mmu_isp>;
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syscon = <&scm_conf 0x6c>;
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ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
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#clock-cells = <1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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bandgap: bandgap@48002524 {
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reg = <0x48002524 0x4>;
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compatible = "ti,omap34xx-bandgap";
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#thermal-sensor-cells = <0>;
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};
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target-module@480cb000 {
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compatible = "ti,sysc-omap3430-sr", "ti,sysc";
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ti,hwmods = "smartreflex_core";
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reg = <0x480cb024 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
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clocks = <&sr2_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480cb000 0x001000>;
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smartreflex_core: smartreflex@0 {
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compatible = "ti,omap3-smartreflex-core";
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reg = <0 0x400>;
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interrupts = <19>;
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};
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};
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target-module@480c9000 {
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compatible = "ti,sysc-omap3430-sr", "ti,sysc";
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ti,hwmods = "smartreflex_mpu_iva";
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reg = <0x480c9024 0x4>;
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reg-names = "sysc";
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ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
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clocks = <&sr1_fck>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x480c9000 0x001000>;
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smartreflex_mpu_iva: smartreflex@480c9000 {
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compatible = "ti,omap3-smartreflex-mpu-iva";
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reg = <0 0x400>;
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interrupts = <18>;
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};
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};
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/*
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* On omap34xx the OCP registers do not seem to be accessible
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* at all unlike on 36xx. Maybe SGX is permanently set to
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* "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
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* write-only at 0x50000e10. We detect SGX based on the SGX
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* revision register instead of the unreadable OCP revision
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* register. Also note that on early 34xx es1 revision there
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* are also different clocks, but we do not have any dts users
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* for it.
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*/
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sgx_module: target-module@50000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x50000014 0x4>;
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reg-names = "rev";
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clocks = <&sgx_fck>, <&sgx_ick>;
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clock-names = "fck", "ick";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x50000000 0x4000>;
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/*
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* Closed source PowerVR driver, no child device
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* binding or driver in mainline
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*/
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};
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};
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thermal_zones: thermal-zones {
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#include "omap3-cpu-thermal.dtsi"
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};
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};
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&ssi {
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status = "ok";
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clocks = <&ssi_ssr_fck>,
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<&ssi_sst_fck>,
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<&ssi_ick>;
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clock-names = "ssi_ssr_fck",
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"ssi_sst_fck",
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"ssi_ick";
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};
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/include/ "omap34xx-omap36xx-clocks.dtsi"
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/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
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/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
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