4711ba10b1
1/ Since commit 858d4aa7 "isci: Move firmware loading to per PCI device" we have
been silently falling back to built-in defaults for the parameter settings by
skipping the call to scic_oem_parameters_set().
2/ The afe parameters from the firmware were not being honored
3/ The latest oem parameter definition flips the mode_type values which are
now 0: for APC 1: for MPC. For APC we need to make sure all the phys
default to the same address otherwise strict_wide_ports will cause duplicate
domains.
4/ Fix up the driver announcement to indicate the source of the
parameters.
5/ Fix up the sas addresses to be unique per controller (in the fallback case)
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
100 lines
2.3 KiB
C
100 lines
2.3 KiB
C
#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <string.h>
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#include <errno.h>
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#include <asm/types.h>
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#include <strings.h>
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#include <stdint.h>
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#include "create_fw.h"
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#include "../probe_roms.h"
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int write_blob(struct isci_orom *isci_orom)
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{
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FILE *fd;
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int err;
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size_t count;
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fd = fopen(blob_name, "w+");
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if (!fd) {
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perror("Open file for write failed");
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fclose(fd);
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return -EIO;
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}
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count = fwrite(isci_orom, sizeof(struct isci_orom), 1, fd);
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if (count != 1) {
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perror("Write data failed");
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fclose(fd);
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return -EIO;
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}
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fclose(fd);
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return 0;
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}
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void set_binary_values(struct isci_orom *isci_orom)
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{
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int ctrl_idx, phy_idx, port_idx;
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/* setting OROM signature */
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strncpy(isci_orom->hdr.signature, sig, strlen(sig));
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isci_orom->hdr.version = version;
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isci_orom->hdr.total_block_length = sizeof(struct isci_orom);
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isci_orom->hdr.hdr_length = sizeof(struct sci_bios_oem_param_block_hdr);
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isci_orom->hdr.num_elements = num_elements;
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for (ctrl_idx = 0; ctrl_idx < 2; ctrl_idx++) {
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isci_orom->ctrl[ctrl_idx].controller.mode_type = mode_type;
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isci_orom->ctrl[ctrl_idx].controller.max_concurrent_dev_spin_up =
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max_num_concurrent_dev_spin_up;
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isci_orom->ctrl[ctrl_idx].controller.do_enable_ssc =
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enable_ssc;
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for (port_idx = 0; port_idx < 4; port_idx++)
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isci_orom->ctrl[ctrl_idx].ports[port_idx].phy_mask =
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phy_mask[ctrl_idx][port_idx];
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for (phy_idx = 0; phy_idx < 4; phy_idx++) {
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].sas_address.high =
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(__u32)(sas_addr[ctrl_idx][phy_idx] >> 32);
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].sas_address.low =
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(__u32)(sas_addr[ctrl_idx][phy_idx]);
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control0 =
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afe_tx_amp_control0;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control1 =
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afe_tx_amp_control1;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control2 =
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afe_tx_amp_control2;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control3 =
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afe_tx_amp_control3;
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}
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}
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}
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int main(void)
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{
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int err;
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struct isci_orom *isci_orom;
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isci_orom = malloc(sizeof(struct isci_orom));
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memset(isci_orom, 0, sizeof(struct isci_orom));
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set_binary_values(isci_orom);
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err = write_blob(isci_orom);
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if (err < 0) {
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free(isci_orom);
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return err;
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}
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free(isci_orom);
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return 0;
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}
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