efc3624c94
We have several instances of inline assembly code that use the addic or addic. instructions, but don't include XER in the list of clobbers. The addic and addic. instructions affect the carry bit, which is in the XER register. This adds "xer" to the list of clobbers for those inline asm statements that use addic or addic. and didn't already have it. Signed-off-by: Paul Mackerras <paulus@samba.org>
296 lines
6.6 KiB
C
296 lines
6.6 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#ifdef __KERNEL__
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/*
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* Simple spin lock operations.
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*
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* Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
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* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
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* Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
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* Rework to support virtual processors
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*
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* Type of int is used as a full 64b word is not necessary.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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#include <linux/irqflags.h>
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#ifdef CONFIG_PPC64
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#include <asm/paca.h>
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#include <asm/hvcall.h>
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#include <asm/iseries/hv_call.h>
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#endif
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#include <asm/asm-compat.h>
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#include <asm/synch.h>
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#define __raw_spin_is_locked(x) ((x)->slock != 0)
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#ifdef CONFIG_PPC64
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/* use 0x800000yy when locked, where yy == CPU number */
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#define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
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#else
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#define LOCK_TOKEN 1
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#endif
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#if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
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#define CLEAR_IO_SYNC (get_paca()->io_sync = 0)
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#define SYNC_IO do { \
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if (unlikely(get_paca()->io_sync)) { \
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mb(); \
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get_paca()->io_sync = 0; \
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} \
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} while (0)
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#else
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#define CLEAR_IO_SYNC
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#define SYNC_IO
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#endif
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/*
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* This returns the old value in the lock, so we succeeded
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* in getting the lock if the return value is 0.
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*/
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static inline unsigned long __spin_trylock(raw_spinlock_t *lock)
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{
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unsigned long tmp, token;
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token = LOCK_TOKEN;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2\n\
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cmpwi 0,%0,0\n\
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bne- 2f\n\
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stwcx. %1,0,%2\n\
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bne- 1b\n\
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isync\n\
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2:" : "=&r" (tmp)
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: "r" (token), "r" (&lock->slock)
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: "cr0", "memory");
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return tmp;
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}
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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CLEAR_IO_SYNC;
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return __spin_trylock(lock) == 0;
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}
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/*
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* On a system with shared processors (that is, where a physical
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* processor is multiplexed between several virtual processors),
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* there is no point spinning on a lock if the holder of the lock
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* isn't currently scheduled on a physical processor. Instead
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* we detect this situation and ask the hypervisor to give the
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* rest of our timeslice to the lock holder.
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*
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* So that we can tell which virtual processor is holding a lock,
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* we put 0x80000000 | smp_processor_id() in the lock when it is
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* held. Conveniently, we have a word in the paca that holds this
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* value.
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*/
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#if defined(CONFIG_PPC_SPLPAR) || defined(CONFIG_PPC_ISERIES)
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/* We only yield to the hypervisor if we are in shared processor mode */
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#define SHARED_PROCESSOR (get_lppaca()->shared_proc)
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extern void __spin_yield(raw_spinlock_t *lock);
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extern void __rw_yield(raw_rwlock_t *lock);
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#else /* SPLPAR || ISERIES */
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#define __spin_yield(x) barrier()
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#define __rw_yield(x) barrier()
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#define SHARED_PROCESSOR 0
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#endif
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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CLEAR_IO_SYNC;
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while (1) {
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if (likely(__spin_trylock(lock) == 0))
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break;
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do {
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HMT_low();
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if (SHARED_PROCESSOR)
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__spin_yield(lock);
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} while (unlikely(lock->slock != 0));
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HMT_medium();
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}
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}
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static inline
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void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
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{
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unsigned long flags_dis;
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CLEAR_IO_SYNC;
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while (1) {
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if (likely(__spin_trylock(lock) == 0))
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break;
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local_save_flags(flags_dis);
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local_irq_restore(flags);
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do {
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HMT_low();
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if (SHARED_PROCESSOR)
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__spin_yield(lock);
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} while (unlikely(lock->slock != 0));
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HMT_medium();
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local_irq_restore(flags_dis);
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}
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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SYNC_IO;
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__asm__ __volatile__("# __raw_spin_unlock\n\t"
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LWSYNC_ON_SMP: : :"memory");
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lock->slock = 0;
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}
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#ifdef CONFIG_PPC64
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extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
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#else
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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#endif
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
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#define __raw_write_can_lock(rw) (!(rw)->lock)
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#ifdef CONFIG_PPC64
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#define __DO_SIGN_EXTEND "extsw %0,%0\n"
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#define WRLOCK_TOKEN LOCK_TOKEN /* it's negative */
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#else
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#define __DO_SIGN_EXTEND
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#define WRLOCK_TOKEN (-1)
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#endif
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/*
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* This returns the old value in the lock + 1,
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* so we got a read lock if the return value is > 0.
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*/
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static inline long __read_trylock(raw_rwlock_t *rw)
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{
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long tmp;
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__asm__ __volatile__(
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"1: lwarx %0,0,%1\n"
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__DO_SIGN_EXTEND
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" addic. %0,%0,1\n\
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ble- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b\n\
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isync\n\
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2:" : "=&r" (tmp)
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: "r" (&rw->lock)
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: "cr0", "xer", "memory");
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return tmp;
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}
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/*
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* This returns the old value in the lock,
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* so we got the write lock if the return value is 0.
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*/
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static inline long __write_trylock(raw_rwlock_t *rw)
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{
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long tmp, token;
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token = WRLOCK_TOKEN;
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__asm__ __volatile__(
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"1: lwarx %0,0,%2\n\
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cmpwi 0,%0,0\n\
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bne- 2f\n"
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PPC405_ERR77(0,%1)
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" stwcx. %1,0,%2\n\
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bne- 1b\n\
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isync\n\
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2:" : "=&r" (tmp)
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: "r" (token), "r" (&rw->lock)
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: "cr0", "memory");
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return tmp;
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}
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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while (1) {
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if (likely(__read_trylock(rw) > 0))
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break;
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do {
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HMT_low();
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if (SHARED_PROCESSOR)
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__rw_yield(rw);
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} while (unlikely(rw->lock < 0));
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HMT_medium();
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}
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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while (1) {
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if (likely(__write_trylock(rw) == 0))
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break;
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do {
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HMT_low();
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if (SHARED_PROCESSOR)
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__rw_yield(rw);
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} while (unlikely(rw->lock != 0));
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HMT_medium();
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}
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}
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static inline int __raw_read_trylock(raw_rwlock_t *rw)
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{
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return __read_trylock(rw) > 0;
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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return __write_trylock(rw) == 0;
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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long tmp;
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__asm__ __volatile__(
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"# read_unlock\n\t"
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LWSYNC_ON_SMP
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"1: lwarx %0,0,%1\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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: "=&r"(tmp)
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: "r"(&rw->lock)
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: "cr0", "xer", "memory");
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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__asm__ __volatile__("# write_unlock\n\t"
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LWSYNC_ON_SMP: : :"memory");
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rw->lock = 0;
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}
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#define _raw_spin_relax(lock) __spin_yield(lock)
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#define _raw_read_relax(lock) __rw_yield(lock)
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#define _raw_write_relax(lock) __rw_yield(lock)
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#endif /* __KERNEL__ */
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#endif /* __ASM_SPINLOCK_H */
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