![Pawel Moll](/assets/img/avatar_default.png)
This patch makes Versatile Express use the common clock framework instead of the plat-versatile implementation. It defines clock provider for VE's OSCs (clock generators) and registers all required fixed and variable clock sources (for both motherboard and core tile). This is a simple conversion of the existing state and will be extended (and migrated to drivers/clk) in the near future. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
170 lines
4.2 KiB
C
170 lines
4.2 KiB
C
#ifndef __MACH_MOTHERBOARD_H
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#define __MACH_MOTHERBOARD_H
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#include <linux/clk-provider.h>
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/*
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* Physical addresses, offset from V2M_PA_CS0-3
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*/
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#define V2M_NOR0 (V2M_PA_CS0)
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#define V2M_NOR1 (V2M_PA_CS1)
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#define V2M_SRAM (V2M_PA_CS2)
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#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
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#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
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#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
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/*
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* Physical addresses, offset from V2M_PA_CS7
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*/
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#define V2M_SYSREGS (V2M_PA_CS7 + 0x00000000)
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#define V2M_SYSCTL (V2M_PA_CS7 + 0x00001000)
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#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + 0x00002000)
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#define V2M_AACI (V2M_PA_CS7 + 0x00004000)
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#define V2M_MMCI (V2M_PA_CS7 + 0x00005000)
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#define V2M_KMI0 (V2M_PA_CS7 + 0x00006000)
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#define V2M_KMI1 (V2M_PA_CS7 + 0x00007000)
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#define V2M_UART0 (V2M_PA_CS7 + 0x00009000)
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#define V2M_UART1 (V2M_PA_CS7 + 0x0000a000)
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#define V2M_UART2 (V2M_PA_CS7 + 0x0000b000)
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#define V2M_UART3 (V2M_PA_CS7 + 0x0000c000)
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#define V2M_WDT (V2M_PA_CS7 + 0x0000f000)
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#define V2M_TIMER01 (V2M_PA_CS7 + 0x00011000)
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#define V2M_TIMER23 (V2M_PA_CS7 + 0x00012000)
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#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + 0x00016000)
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#define V2M_RTC (V2M_PA_CS7 + 0x00017000)
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#define V2M_CF (V2M_PA_CS7 + 0x0001a000)
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#define V2M_CLCD (V2M_PA_CS7 + 0x0001f000)
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/*
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* Offsets from SYSREGS base
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*/
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#define V2M_SYS_ID 0x000
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#define V2M_SYS_SW 0x004
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#define V2M_SYS_LED 0x008
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#define V2M_SYS_100HZ 0x024
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#define V2M_SYS_FLAGS 0x030
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#define V2M_SYS_FLAGSSET 0x030
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#define V2M_SYS_FLAGSCLR 0x034
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#define V2M_SYS_NVFLAGS 0x038
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#define V2M_SYS_NVFLAGSSET 0x038
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#define V2M_SYS_NVFLAGSCLR 0x03c
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#define V2M_SYS_MCI 0x048
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#define V2M_SYS_FLASH 0x03c
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#define V2M_SYS_CFGSW 0x058
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#define V2M_SYS_24MHZ 0x05c
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#define V2M_SYS_MISC 0x060
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#define V2M_SYS_DMA 0x064
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#define V2M_SYS_PROCID0 0x084
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#define V2M_SYS_PROCID1 0x088
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#define V2M_SYS_CFGDATA 0x0a0
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#define V2M_SYS_CFGCTRL 0x0a4
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#define V2M_SYS_CFGSTAT 0x0a8
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/*
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* Interrupts. Those in {} are for AMBA devices
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*/
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#define IRQ_V2M_WDT { (32 + 0) }
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#define IRQ_V2M_TIMER0 (32 + 2)
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#define IRQ_V2M_TIMER1 (32 + 2)
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#define IRQ_V2M_TIMER2 (32 + 3)
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#define IRQ_V2M_TIMER3 (32 + 3)
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#define IRQ_V2M_RTC { (32 + 4) }
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#define IRQ_V2M_UART0 { (32 + 5) }
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#define IRQ_V2M_UART1 { (32 + 6) }
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#define IRQ_V2M_UART2 { (32 + 7) }
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#define IRQ_V2M_UART3 { (32 + 8) }
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#define IRQ_V2M_MMCI { (32 + 9), (32 + 10) }
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#define IRQ_V2M_AACI { (32 + 11) }
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#define IRQ_V2M_KMI0 { (32 + 12) }
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#define IRQ_V2M_KMI1 { (32 + 13) }
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#define IRQ_V2M_CLCD { (32 + 14) }
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#define IRQ_V2M_LAN9118 (32 + 15)
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#define IRQ_V2M_ISP1761 (32 + 16)
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#define IRQ_V2M_PCIE (32 + 17)
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/*
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* Configuration
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*/
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#define SYS_CFG_START (1 << 31)
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#define SYS_CFG_WRITE (1 << 30)
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#define SYS_CFG_OSC (1 << 20)
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#define SYS_CFG_VOLT (2 << 20)
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#define SYS_CFG_AMP (3 << 20)
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#define SYS_CFG_TEMP (4 << 20)
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#define SYS_CFG_RESET (5 << 20)
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#define SYS_CFG_SCC (6 << 20)
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#define SYS_CFG_MUXFPGA (7 << 20)
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#define SYS_CFG_SHUTDOWN (8 << 20)
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#define SYS_CFG_REBOOT (9 << 20)
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#define SYS_CFG_DVIMODE (11 << 20)
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#define SYS_CFG_POWER (12 << 20)
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#define SYS_CFG_SITE(n) ((n) << 16)
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#define SYS_CFG_SITE_MB 0
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#define SYS_CFG_SITE_DB1 1
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#define SYS_CFG_SITE_DB2 2
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#define SYS_CFG_STACK(n) ((n) << 12)
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#define SYS_CFG_ERR (1 << 1)
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#define SYS_CFG_COMPLETE (1 << 0)
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int v2m_cfg_write(u32 devfn, u32 data);
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int v2m_cfg_read(u32 devfn, u32 *data);
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void v2m_flags_set(u32 data);
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/*
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* Miscellaneous
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*/
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#define SYS_MISC_MASTERSITE (1 << 14)
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#define SYS_PROCIDx_HBI_MASK 0xfff
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int v2m_get_master_site(void);
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/*
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* Core tile IDs
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*/
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#define V2M_CT_ID_CA9 0x0c000191
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#define V2M_CT_ID_UNSUPPORTED 0xff000191
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#define V2M_CT_ID_MASK 0xff000fff
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struct ct_desc {
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u32 id;
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const char *name;
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void (*map_io)(void);
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void (*init_early)(void);
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void (*init_irq)(void);
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void (*init_tile)(void);
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#ifdef CONFIG_SMP
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void (*init_cpu_map)(void);
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void (*smp_enable)(unsigned int);
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#endif
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};
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extern struct ct_desc *ct_desc;
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/*
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* OSC clock provider
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*/
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struct v2m_osc {
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struct clk_hw hw;
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u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
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u8 stack; /* board stack position */
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u16 osc;
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unsigned long rate_min;
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unsigned long rate_max;
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unsigned long rate_default;
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};
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#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
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struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
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#endif
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