![Christoph Hellwig](/assets/img/avatar_default.png)
As far as the device is concerned the dma address is the physical
address. There is no need to convert it to a physical address,
especially not using dma-direct internals that are not available
to drivers and which will interact badly with IOMMUs. Last but not
least the commit introducing it claimed to just fix a type issue,
but actually changed behavior.
Fixes: 6e37ccf78a
("firmware: qcom_scm: Use proper types for dma mappings")
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/20200414123136.441454-1-hch@lst.de
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
1173 lines
28 KiB
C
1173 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
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* Copyright (C) 2015 Linaro Ltd.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/cpumask.h>
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#include <linux/export.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/qcom_scm.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/reset-controller.h>
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#include <linux/arm-smccc.h>
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#include "qcom_scm.h"
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static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
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module_param(download_mode, bool, 0);
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#define SCM_HAS_CORE_CLK BIT(0)
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#define SCM_HAS_IFACE_CLK BIT(1)
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#define SCM_HAS_BUS_CLK BIT(2)
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struct qcom_scm {
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struct device *dev;
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struct clk *core_clk;
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struct clk *iface_clk;
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struct clk *bus_clk;
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struct reset_controller_dev reset;
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u64 dload_mode_addr;
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};
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struct qcom_scm_current_perm_info {
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__le32 vmid;
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__le32 perm;
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__le64 ctx;
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__le32 ctx_size;
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__le32 unused;
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};
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struct qcom_scm_mem_map_info {
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__le64 mem_addr;
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__le64 mem_size;
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};
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#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
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#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
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#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
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#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
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#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
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#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
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#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
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#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
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struct qcom_scm_wb_entry {
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int flag;
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void *entry;
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};
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static struct qcom_scm_wb_entry qcom_scm_wb[] = {
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
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{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
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};
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static const char *qcom_scm_convention_names[] = {
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[SMC_CONVENTION_UNKNOWN] = "unknown",
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[SMC_CONVENTION_ARM_32] = "smc arm 32",
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[SMC_CONVENTION_ARM_64] = "smc arm 64",
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[SMC_CONVENTION_LEGACY] = "smc legacy",
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};
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static struct qcom_scm *__scm;
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static int qcom_scm_clk_enable(void)
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{
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int ret;
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ret = clk_prepare_enable(__scm->core_clk);
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if (ret)
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goto bail;
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ret = clk_prepare_enable(__scm->iface_clk);
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if (ret)
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goto disable_core;
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ret = clk_prepare_enable(__scm->bus_clk);
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if (ret)
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goto disable_iface;
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return 0;
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disable_iface:
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clk_disable_unprepare(__scm->iface_clk);
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disable_core:
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clk_disable_unprepare(__scm->core_clk);
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bail:
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return ret;
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}
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static void qcom_scm_clk_disable(void)
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{
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clk_disable_unprepare(__scm->core_clk);
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clk_disable_unprepare(__scm->iface_clk);
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clk_disable_unprepare(__scm->bus_clk);
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}
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static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
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u32 cmd_id);
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enum qcom_scm_convention qcom_scm_convention;
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static bool has_queried __read_mostly;
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static DEFINE_SPINLOCK(query_lock);
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static void __query_convention(void)
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{
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unsigned long flags;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_INFO,
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.cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
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.args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
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QCOM_SCM_INFO_IS_CALL_AVAIL) |
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(ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
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.arginfo = QCOM_SCM_ARGS(1),
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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int ret;
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spin_lock_irqsave(&query_lock, flags);
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if (has_queried)
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goto out;
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qcom_scm_convention = SMC_CONVENTION_ARM_64;
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// Device isn't required as there is only one argument - no device
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// needed to dma_map_single to secure world
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ret = scm_smc_call(NULL, &desc, &res, true);
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if (!ret && res.result[0] == 1)
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goto out;
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qcom_scm_convention = SMC_CONVENTION_ARM_32;
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ret = scm_smc_call(NULL, &desc, &res, true);
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if (!ret && res.result[0] == 1)
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goto out;
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qcom_scm_convention = SMC_CONVENTION_LEGACY;
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out:
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has_queried = true;
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spin_unlock_irqrestore(&query_lock, flags);
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pr_info("qcom_scm: convention: %s\n",
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qcom_scm_convention_names[qcom_scm_convention]);
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}
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static inline enum qcom_scm_convention __get_convention(void)
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{
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if (unlikely(!has_queried))
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__query_convention();
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return qcom_scm_convention;
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}
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/**
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* qcom_scm_call() - Invoke a syscall in the secure world
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* @dev: device
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @desc: Descriptor structure containing arguments and return values
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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* This should *only* be called in pre-emptible context.
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*/
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static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
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struct qcom_scm_res *res)
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{
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might_sleep();
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switch (__get_convention()) {
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case SMC_CONVENTION_ARM_32:
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case SMC_CONVENTION_ARM_64:
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return scm_smc_call(dev, desc, res, false);
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case SMC_CONVENTION_LEGACY:
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return scm_legacy_call(dev, desc, res);
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default:
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pr_err("Unknown current SCM calling convention.\n");
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return -EINVAL;
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}
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}
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/**
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* qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
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* @dev: device
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* @svc_id: service identifier
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* @cmd_id: command identifier
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* @desc: Descriptor structure containing arguments and return values
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* @res: Structure containing results from SMC/HVC call
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*
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* Sends a command to the SCM and waits for the command to finish processing.
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* This can be called in atomic context.
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*/
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static int qcom_scm_call_atomic(struct device *dev,
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const struct qcom_scm_desc *desc,
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struct qcom_scm_res *res)
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{
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switch (__get_convention()) {
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case SMC_CONVENTION_ARM_32:
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case SMC_CONVENTION_ARM_64:
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return scm_smc_call(dev, desc, res, true);
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case SMC_CONVENTION_LEGACY:
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return scm_legacy_call_atomic(dev, desc, res);
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default:
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pr_err("Unknown current SCM calling convention.\n");
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return -EINVAL;
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}
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}
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static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
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u32 cmd_id)
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{
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_INFO,
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.cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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desc.arginfo = QCOM_SCM_ARGS(1);
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switch (__get_convention()) {
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case SMC_CONVENTION_ARM_32:
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case SMC_CONVENTION_ARM_64:
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desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
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(ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
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break;
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case SMC_CONVENTION_LEGACY:
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desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id);
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break;
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default:
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pr_err("Unknown SMC convention being used\n");
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return -EINVAL;
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}
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ret = qcom_scm_call(dev, &desc, &res);
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return ret ? : res.result[0];
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}
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/**
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* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the Linux entry point for the SCM to transfer control to when coming
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* out of a power down. CPU power down may be executed on cpuidle or hotplug.
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*/
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int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
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{
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int ret;
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int flags = 0;
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int cpu;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_SET_ADDR,
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.arginfo = QCOM_SCM_ARGS(2),
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};
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/*
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* Reassign only if we are switching from hotplug entry point
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* to cpuidle entry point or vice versa.
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*/
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for_each_cpu(cpu, cpus) {
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if (entry == qcom_scm_wb[cpu].entry)
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continue;
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flags |= qcom_scm_wb[cpu].flag;
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}
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/* No change in entry function */
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if (!flags)
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return 0;
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desc.args[0] = flags;
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desc.args[1] = virt_to_phys(entry);
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ret = qcom_scm_call(__scm->dev, &desc, NULL);
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if (!ret) {
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for_each_cpu(cpu, cpus)
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qcom_scm_wb[cpu].entry = entry;
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}
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return ret;
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}
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EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
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/**
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* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
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* @entry: Entry point function for the cpus
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* @cpus: The cpumask of cpus that will use the entry point
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*
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* Set the cold boot address of the cpus. Any cpu outside the supported
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* range would be removed from the cpu present mask.
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*/
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int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
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{
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int flags = 0;
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int cpu;
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int scm_cb_flags[] = {
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QCOM_SCM_FLAG_COLDBOOT_CPU0,
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QCOM_SCM_FLAG_COLDBOOT_CPU1,
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QCOM_SCM_FLAG_COLDBOOT_CPU2,
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QCOM_SCM_FLAG_COLDBOOT_CPU3,
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};
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_SET_ADDR,
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.arginfo = QCOM_SCM_ARGS(2),
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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if (!cpus || (cpus && cpumask_empty(cpus)))
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return -EINVAL;
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for_each_cpu(cpu, cpus) {
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if (cpu < ARRAY_SIZE(scm_cb_flags))
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flags |= scm_cb_flags[cpu];
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else
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set_cpu_present(cpu, false);
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}
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desc.args[0] = flags;
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desc.args[1] = virt_to_phys(entry);
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return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
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}
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EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
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/**
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* qcom_scm_cpu_power_down() - Power down the cpu
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* @flags - Flags to flush cache
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*
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* This is an end point to power down cpu. If there was a pending interrupt,
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* the control would return from this function, otherwise, the cpu jumps to the
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* warm boot entry point set for this cpu upon reset.
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*/
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void qcom_scm_cpu_power_down(u32 flags)
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{
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_TERMINATE_PC,
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.args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
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.arginfo = QCOM_SCM_ARGS(1),
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
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}
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EXPORT_SYMBOL(qcom_scm_cpu_power_down);
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int qcom_scm_set_remote_state(u32 state, u32 id)
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{
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
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.arginfo = QCOM_SCM_ARGS(2),
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.args[0] = state,
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.args[1] = id,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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int ret;
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ret = qcom_scm_call(__scm->dev, &desc, &res);
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return ret ? : res.result[0];
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}
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EXPORT_SYMBOL(qcom_scm_set_remote_state);
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static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
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{
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_BOOT,
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.cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
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.arginfo = QCOM_SCM_ARGS(2),
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.args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
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return qcom_scm_call(__scm->dev, &desc, NULL);
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}
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static void qcom_scm_set_download_mode(bool enable)
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{
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bool avail;
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int ret = 0;
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avail = __qcom_scm_is_call_available(__scm->dev,
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QCOM_SCM_SVC_BOOT,
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QCOM_SCM_BOOT_SET_DLOAD_MODE);
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if (avail) {
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ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
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} else if (__scm->dload_mode_addr) {
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ret = qcom_scm_io_writel(__scm->dload_mode_addr,
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enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
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} else {
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dev_err(__scm->dev,
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"No available mechanism for setting download mode\n");
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}
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if (ret)
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dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
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}
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/**
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* qcom_scm_pas_init_image() - Initialize peripheral authentication service
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* state machine for a given peripheral, using the
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* metadata
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* @peripheral: peripheral id
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* @metadata: pointer to memory containing ELF header, program header table
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* and optional blob of data used for authenticating the metadata
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* and the rest of the firmware
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* @size: size of the metadata
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*
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* Returns 0 on success.
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*/
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int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
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{
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dma_addr_t mdata_phys;
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void *mdata_buf;
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int ret;
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struct qcom_scm_desc desc = {
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.svc = QCOM_SCM_SVC_PIL,
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.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
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.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
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.args[0] = peripheral,
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.owner = ARM_SMCCC_OWNER_SIP,
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};
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struct qcom_scm_res res;
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/*
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* During the scm call memory protection will be enabled for the meta
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* data blob, so make sure it's physically contiguous, 4K aligned and
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* non-cachable to avoid XPU violations.
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*/
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mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
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GFP_KERNEL);
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if (!mdata_buf) {
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dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
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return -ENOMEM;
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}
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memcpy(mdata_buf, metadata, size);
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ret = qcom_scm_clk_enable();
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if (ret)
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goto free_metadata;
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desc.args[1] = mdata_phys;
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ret = qcom_scm_call(__scm->dev, &desc, &res);
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qcom_scm_clk_disable();
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free_metadata:
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|
dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
|
|
|
|
return ret ? : res.result[0];
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_pas_init_image);
|
|
|
|
/**
|
|
* qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
|
|
* for firmware loading
|
|
* @peripheral: peripheral id
|
|
* @addr: start address of memory area to prepare
|
|
* @size: size of the memory area to prepare
|
|
*
|
|
* Returns 0 on success.
|
|
*/
|
|
int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
|
|
{
|
|
int ret;
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_PIL,
|
|
.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
|
|
.arginfo = QCOM_SCM_ARGS(3),
|
|
.args[0] = peripheral,
|
|
.args[1] = addr,
|
|
.args[2] = size,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
|
|
ret = qcom_scm_clk_enable();
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
qcom_scm_clk_disable();
|
|
|
|
return ret ? : res.result[0];
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
|
|
|
|
/**
|
|
* qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
|
|
* and reset the remote processor
|
|
* @peripheral: peripheral id
|
|
*
|
|
* Return 0 on success.
|
|
*/
|
|
int qcom_scm_pas_auth_and_reset(u32 peripheral)
|
|
{
|
|
int ret;
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_PIL,
|
|
.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
|
|
.arginfo = QCOM_SCM_ARGS(1),
|
|
.args[0] = peripheral,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
|
|
ret = qcom_scm_clk_enable();
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
qcom_scm_clk_disable();
|
|
|
|
return ret ? : res.result[0];
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
|
|
|
|
/**
|
|
* qcom_scm_pas_shutdown() - Shut down the remote processor
|
|
* @peripheral: peripheral id
|
|
*
|
|
* Returns 0 on success.
|
|
*/
|
|
int qcom_scm_pas_shutdown(u32 peripheral)
|
|
{
|
|
int ret;
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_PIL,
|
|
.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
|
|
.arginfo = QCOM_SCM_ARGS(1),
|
|
.args[0] = peripheral,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
|
|
ret = qcom_scm_clk_enable();
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
|
|
qcom_scm_clk_disable();
|
|
|
|
return ret ? : res.result[0];
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_pas_shutdown);
|
|
|
|
/**
|
|
* qcom_scm_pas_supported() - Check if the peripheral authentication service is
|
|
* available for the given peripherial
|
|
* @peripheral: peripheral id
|
|
*
|
|
* Returns true if PAS is supported for this peripheral, otherwise false.
|
|
*/
|
|
bool qcom_scm_pas_supported(u32 peripheral)
|
|
{
|
|
int ret;
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_PIL,
|
|
.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
|
|
.arginfo = QCOM_SCM_ARGS(1),
|
|
.args[0] = peripheral,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
|
|
ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
|
|
QCOM_SCM_PIL_PAS_IS_SUPPORTED);
|
|
if (ret <= 0)
|
|
return false;
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
|
|
return ret ? false : !!res.result[0];
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_pas_supported);
|
|
|
|
static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_PIL,
|
|
.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
|
|
.arginfo = QCOM_SCM_ARGS(2),
|
|
.args[0] = reset,
|
|
.args[1] = 0,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
int ret;
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
|
|
return ret ? : res.result[0];
|
|
}
|
|
|
|
static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
|
|
unsigned long idx)
|
|
{
|
|
if (idx != 0)
|
|
return -EINVAL;
|
|
|
|
return __qcom_scm_pas_mss_reset(__scm->dev, 1);
|
|
}
|
|
|
|
static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
|
|
unsigned long idx)
|
|
{
|
|
if (idx != 0)
|
|
return -EINVAL;
|
|
|
|
return __qcom_scm_pas_mss_reset(__scm->dev, 0);
|
|
}
|
|
|
|
static const struct reset_control_ops qcom_scm_pas_reset_ops = {
|
|
.assert = qcom_scm_pas_reset_assert,
|
|
.deassert = qcom_scm_pas_reset_deassert,
|
|
};
|
|
|
|
int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_IO,
|
|
.cmd = QCOM_SCM_IO_READ,
|
|
.arginfo = QCOM_SCM_ARGS(1),
|
|
.args[0] = addr,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
int ret;
|
|
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
if (ret >= 0)
|
|
*val = res.result[0];
|
|
|
|
return ret < 0 ? ret : 0;
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_io_readl);
|
|
|
|
int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_IO,
|
|
.cmd = QCOM_SCM_IO_WRITE,
|
|
.arginfo = QCOM_SCM_ARGS(2),
|
|
.args[0] = addr,
|
|
.args[1] = val,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
|
|
|
|
return qcom_scm_call(__scm->dev, &desc, NULL);
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_io_writel);
|
|
|
|
/**
|
|
* qcom_scm_restore_sec_cfg_available() - Check if secure environment
|
|
* supports restore security config interface.
|
|
*
|
|
* Return true if restore-cfg interface is supported, false if not.
|
|
*/
|
|
bool qcom_scm_restore_sec_cfg_available(void)
|
|
{
|
|
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
|
|
QCOM_SCM_MP_RESTORE_SEC_CFG);
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);
|
|
|
|
int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_MP,
|
|
.cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
|
|
.arginfo = QCOM_SCM_ARGS(2),
|
|
.args[0] = device_id,
|
|
.args[1] = spare,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
int ret;
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
|
|
return ret ? : res.result[0];
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
|
|
|
|
int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_MP,
|
|
.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
|
|
.arginfo = QCOM_SCM_ARGS(1),
|
|
.args[0] = spare,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
int ret;
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
|
|
if (size)
|
|
*size = res.result[0];
|
|
|
|
return ret ? : res.result[1];
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
|
|
|
|
int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_MP,
|
|
.cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
|
|
.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
|
|
QCOM_SCM_VAL),
|
|
.args[0] = addr,
|
|
.args[1] = size,
|
|
.args[2] = spare,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
int ret;
|
|
|
|
desc.args[0] = addr;
|
|
desc.args[1] = size;
|
|
desc.args[2] = spare;
|
|
desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
|
|
QCOM_SCM_VAL);
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, NULL);
|
|
|
|
/* the pg table has been initialized already, ignore the error */
|
|
if (ret == -EPERM)
|
|
ret = 0;
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
|
|
|
|
static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
|
|
size_t mem_sz, phys_addr_t src, size_t src_sz,
|
|
phys_addr_t dest, size_t dest_sz)
|
|
{
|
|
int ret;
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_MP,
|
|
.cmd = QCOM_SCM_MP_ASSIGN,
|
|
.arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
|
|
QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
|
|
QCOM_SCM_VAL, QCOM_SCM_VAL),
|
|
.args[0] = mem_region,
|
|
.args[1] = mem_sz,
|
|
.args[2] = src,
|
|
.args[3] = src_sz,
|
|
.args[4] = dest,
|
|
.args[5] = dest_sz,
|
|
.args[6] = 0,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
|
|
ret = qcom_scm_call(dev, &desc, &res);
|
|
|
|
return ret ? : res.result[0];
|
|
}
|
|
|
|
/**
|
|
* qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
|
|
* @mem_addr: mem region whose ownership need to be reassigned
|
|
* @mem_sz: size of the region.
|
|
* @srcvm: vmid for current set of owners, each set bit in
|
|
* flag indicate a unique owner
|
|
* @newvm: array having new owners and corresponding permission
|
|
* flags
|
|
* @dest_cnt: number of owners in next set.
|
|
*
|
|
* Return negative errno on failure or 0 on success with @srcvm updated.
|
|
*/
|
|
int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
|
|
unsigned int *srcvm,
|
|
const struct qcom_scm_vmperm *newvm,
|
|
unsigned int dest_cnt)
|
|
{
|
|
struct qcom_scm_current_perm_info *destvm;
|
|
struct qcom_scm_mem_map_info *mem_to_map;
|
|
phys_addr_t mem_to_map_phys;
|
|
phys_addr_t dest_phys;
|
|
dma_addr_t ptr_phys;
|
|
size_t mem_to_map_sz;
|
|
size_t dest_sz;
|
|
size_t src_sz;
|
|
size_t ptr_sz;
|
|
int next_vm;
|
|
__le32 *src;
|
|
void *ptr;
|
|
int ret, i, b;
|
|
unsigned long srcvm_bits = *srcvm;
|
|
|
|
src_sz = hweight_long(srcvm_bits) * sizeof(*src);
|
|
mem_to_map_sz = sizeof(*mem_to_map);
|
|
dest_sz = dest_cnt * sizeof(*destvm);
|
|
ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
|
|
ALIGN(dest_sz, SZ_64);
|
|
|
|
ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
|
|
if (!ptr)
|
|
return -ENOMEM;
|
|
|
|
/* Fill source vmid detail */
|
|
src = ptr;
|
|
i = 0;
|
|
for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG)
|
|
src[i++] = cpu_to_le32(b);
|
|
|
|
/* Fill details of mem buff to map */
|
|
mem_to_map = ptr + ALIGN(src_sz, SZ_64);
|
|
mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
|
|
mem_to_map->mem_addr = cpu_to_le64(mem_addr);
|
|
mem_to_map->mem_size = cpu_to_le64(mem_sz);
|
|
|
|
next_vm = 0;
|
|
/* Fill details of next vmid detail */
|
|
destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
|
|
dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
|
|
for (i = 0; i < dest_cnt; i++, destvm++, newvm++) {
|
|
destvm->vmid = cpu_to_le32(newvm->vmid);
|
|
destvm->perm = cpu_to_le32(newvm->perm);
|
|
destvm->ctx = 0;
|
|
destvm->ctx_size = 0;
|
|
next_vm |= BIT(newvm->vmid);
|
|
}
|
|
|
|
ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
|
|
ptr_phys, src_sz, dest_phys, dest_sz);
|
|
dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys);
|
|
if (ret) {
|
|
dev_err(__scm->dev,
|
|
"Assign memory protection call failed %d\n", ret);
|
|
return -EINVAL;
|
|
}
|
|
|
|
*srcvm = next_vm;
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_assign_mem);
|
|
|
|
/**
|
|
* qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
|
|
*/
|
|
bool qcom_scm_ocmem_lock_available(void)
|
|
{
|
|
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
|
|
QCOM_SCM_OCMEM_LOCK_CMD);
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
|
|
|
|
/**
|
|
* qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
|
|
* region to the specified initiator
|
|
*
|
|
* @id: tz initiator id
|
|
* @offset: OCMEM offset
|
|
* @size: OCMEM size
|
|
* @mode: access mode (WIDE/NARROW)
|
|
*/
|
|
int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
|
|
u32 mode)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_OCMEM,
|
|
.cmd = QCOM_SCM_OCMEM_LOCK_CMD,
|
|
.args[0] = id,
|
|
.args[1] = offset,
|
|
.args[2] = size,
|
|
.args[3] = mode,
|
|
.arginfo = QCOM_SCM_ARGS(4),
|
|
};
|
|
|
|
return qcom_scm_call(__scm->dev, &desc, NULL);
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_ocmem_lock);
|
|
|
|
/**
|
|
* qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
|
|
* region from the specified initiator
|
|
*
|
|
* @id: tz initiator id
|
|
* @offset: OCMEM offset
|
|
* @size: OCMEM size
|
|
*/
|
|
int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_OCMEM,
|
|
.cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
|
|
.args[0] = id,
|
|
.args[1] = offset,
|
|
.args[2] = size,
|
|
.arginfo = QCOM_SCM_ARGS(3),
|
|
};
|
|
|
|
return qcom_scm_call(__scm->dev, &desc, NULL);
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
|
|
|
|
/**
|
|
* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
|
|
*
|
|
* Return true if HDCP is supported, false if not.
|
|
*/
|
|
bool qcom_scm_hdcp_available(void)
|
|
{
|
|
int ret = qcom_scm_clk_enable();
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
|
|
QCOM_SCM_HDCP_INVOKE);
|
|
|
|
qcom_scm_clk_disable();
|
|
|
|
return ret > 0;
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_hdcp_available);
|
|
|
|
/**
|
|
* qcom_scm_hdcp_req() - Send HDCP request.
|
|
* @req: HDCP request array
|
|
* @req_cnt: HDCP request array count
|
|
* @resp: response buffer passed to SCM
|
|
*
|
|
* Write HDCP register(s) through SCM.
|
|
*/
|
|
int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
|
|
{
|
|
int ret;
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_HDCP,
|
|
.cmd = QCOM_SCM_HDCP_INVOKE,
|
|
.arginfo = QCOM_SCM_ARGS(10),
|
|
.args = {
|
|
req[0].addr,
|
|
req[0].val,
|
|
req[1].addr,
|
|
req[1].val,
|
|
req[2].addr,
|
|
req[2].val,
|
|
req[3].addr,
|
|
req[3].val,
|
|
req[4].addr,
|
|
req[4].val
|
|
},
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
struct qcom_scm_res res;
|
|
|
|
if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
|
|
return -ERANGE;
|
|
|
|
ret = qcom_scm_clk_enable();
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = qcom_scm_call(__scm->dev, &desc, &res);
|
|
*resp = res.result[0];
|
|
|
|
qcom_scm_clk_disable();
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_hdcp_req);
|
|
|
|
int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
|
|
{
|
|
struct qcom_scm_desc desc = {
|
|
.svc = QCOM_SCM_SVC_SMMU_PROGRAM,
|
|
.cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
|
|
.arginfo = QCOM_SCM_ARGS(2),
|
|
.args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL,
|
|
.args[1] = en,
|
|
.owner = ARM_SMCCC_OWNER_SIP,
|
|
};
|
|
|
|
|
|
return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
|
|
|
|
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
|
|
{
|
|
struct device_node *tcsr;
|
|
struct device_node *np = dev->of_node;
|
|
struct resource res;
|
|
u32 offset;
|
|
int ret;
|
|
|
|
tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
|
|
if (!tcsr)
|
|
return 0;
|
|
|
|
ret = of_address_to_resource(tcsr, 0, &res);
|
|
of_node_put(tcsr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
*addr = res.start + offset;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* qcom_scm_is_available() - Checks if SCM is available
|
|
*/
|
|
bool qcom_scm_is_available(void)
|
|
{
|
|
return !!__scm;
|
|
}
|
|
EXPORT_SYMBOL(qcom_scm_is_available);
|
|
|
|
static int qcom_scm_probe(struct platform_device *pdev)
|
|
{
|
|
struct qcom_scm *scm;
|
|
unsigned long clks;
|
|
int ret;
|
|
|
|
scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
|
|
if (!scm)
|
|
return -ENOMEM;
|
|
|
|
ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
clks = (unsigned long)of_device_get_match_data(&pdev->dev);
|
|
|
|
scm->core_clk = devm_clk_get(&pdev->dev, "core");
|
|
if (IS_ERR(scm->core_clk)) {
|
|
if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
|
|
return PTR_ERR(scm->core_clk);
|
|
|
|
if (clks & SCM_HAS_CORE_CLK) {
|
|
dev_err(&pdev->dev, "failed to acquire core clk\n");
|
|
return PTR_ERR(scm->core_clk);
|
|
}
|
|
|
|
scm->core_clk = NULL;
|
|
}
|
|
|
|
scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
|
|
if (IS_ERR(scm->iface_clk)) {
|
|
if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
|
|
return PTR_ERR(scm->iface_clk);
|
|
|
|
if (clks & SCM_HAS_IFACE_CLK) {
|
|
dev_err(&pdev->dev, "failed to acquire iface clk\n");
|
|
return PTR_ERR(scm->iface_clk);
|
|
}
|
|
|
|
scm->iface_clk = NULL;
|
|
}
|
|
|
|
scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
|
|
if (IS_ERR(scm->bus_clk)) {
|
|
if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
|
|
return PTR_ERR(scm->bus_clk);
|
|
|
|
if (clks & SCM_HAS_BUS_CLK) {
|
|
dev_err(&pdev->dev, "failed to acquire bus clk\n");
|
|
return PTR_ERR(scm->bus_clk);
|
|
}
|
|
|
|
scm->bus_clk = NULL;
|
|
}
|
|
|
|
scm->reset.ops = &qcom_scm_pas_reset_ops;
|
|
scm->reset.nr_resets = 1;
|
|
scm->reset.of_node = pdev->dev.of_node;
|
|
ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* vote for max clk rate for highest performance */
|
|
ret = clk_set_rate(scm->core_clk, INT_MAX);
|
|
if (ret)
|
|
return ret;
|
|
|
|
__scm = scm;
|
|
__scm->dev = &pdev->dev;
|
|
|
|
__query_convention();
|
|
|
|
/*
|
|
* If requested enable "download mode", from this point on warmboot
|
|
* will cause the the boot stages to enter download mode, unless
|
|
* disabled below by a clean shutdown/reboot.
|
|
*/
|
|
if (download_mode)
|
|
qcom_scm_set_download_mode(true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void qcom_scm_shutdown(struct platform_device *pdev)
|
|
{
|
|
/* Clean shutdown, disable download mode to allow normal restart */
|
|
if (download_mode)
|
|
qcom_scm_set_download_mode(false);
|
|
}
|
|
|
|
static const struct of_device_id qcom_scm_dt_match[] = {
|
|
{ .compatible = "qcom,scm-apq8064",
|
|
/* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
|
|
},
|
|
{ .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
|
|
SCM_HAS_IFACE_CLK |
|
|
SCM_HAS_BUS_CLK)
|
|
},
|
|
{ .compatible = "qcom,scm-ipq4019" },
|
|
{ .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
|
|
{ .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
|
|
{ .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
|
|
SCM_HAS_IFACE_CLK |
|
|
SCM_HAS_BUS_CLK)
|
|
},
|
|
{ .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
|
|
SCM_HAS_IFACE_CLK |
|
|
SCM_HAS_BUS_CLK)
|
|
},
|
|
{ .compatible = "qcom,scm-msm8996" },
|
|
{ .compatible = "qcom,scm" },
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver qcom_scm_driver = {
|
|
.driver = {
|
|
.name = "qcom_scm",
|
|
.of_match_table = qcom_scm_dt_match,
|
|
},
|
|
.probe = qcom_scm_probe,
|
|
.shutdown = qcom_scm_shutdown,
|
|
};
|
|
|
|
static int __init qcom_scm_init(void)
|
|
{
|
|
return platform_driver_register(&qcom_scm_driver);
|
|
}
|
|
subsys_initcall(qcom_scm_init);
|