![Pierre-Louis Bossart](/assets/img/avatar_default.png)
In the existing SoundWire code, Master Devices are not explicitly represented - only SoundWire Slave Devices are exposed (the use of capital letters follows the SoundWire specification conventions). With the existing code, the bus is handled without using a proper device, and bus->dev typically points to a platform device. The right thing to do as discussed in multiple reviews is use a device for each bus. The sdw_master_device addition is done with minimal internal plumbing and not exposed externally. The existing API based on sdw_bus_master_add() and sdw_bus_master_delete() will deal with the sdw_master_device life cycle, which minimizes changes to existing drivers. Note that the Intel code will be modified in follow-up patches (no impact on any platform since the connection with ASoC is not supported upstream so far). Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com> Acked-by: Jaroslav Kysela <perex@perex.cz> Link: https://lore.kernel.org/r/20200518174322.31561-5-yung-chuan.liao@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
1210 lines
30 KiB
C
1210 lines
30 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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// Copyright(c) 2015-17 Intel Corporation.
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/*
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* Soundwire Intel Master Driver
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*/
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#include <linux/acpi.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <linux/soundwire/sdw.h>
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#include <linux/soundwire/sdw_intel.h>
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#include "cadence_master.h"
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#include "bus.h"
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#include "intel.h"
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/* Intel SHIM Registers Definition */
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#define SDW_SHIM_LCAP 0x0
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#define SDW_SHIM_LCTL 0x4
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#define SDW_SHIM_IPPTR 0x8
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#define SDW_SHIM_SYNC 0xC
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#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
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#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
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#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
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#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
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#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
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#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
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#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
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#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
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#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
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#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
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#define SDW_SHIM_WAKEEN 0x190
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#define SDW_SHIM_WAKESTS 0x192
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#define SDW_SHIM_LCTL_SPA BIT(0)
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#define SDW_SHIM_LCTL_CPA BIT(8)
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#define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F
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#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
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#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
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#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
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#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
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#define SDW_SHIM_SYNC_SYNCGO BIT(24)
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#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
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#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
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#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
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#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
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#define SDW_SHIM_PCMSYCM_DIR BIT(15)
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#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
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#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
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#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
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#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
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#define SDW_SHIM_IOCTL_MIF BIT(0)
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#define SDW_SHIM_IOCTL_CO BIT(1)
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#define SDW_SHIM_IOCTL_COE BIT(2)
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#define SDW_SHIM_IOCTL_DO BIT(3)
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#define SDW_SHIM_IOCTL_DOE BIT(4)
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#define SDW_SHIM_IOCTL_BKE BIT(5)
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#define SDW_SHIM_IOCTL_WPDD BIT(6)
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#define SDW_SHIM_IOCTL_CIBD BIT(8)
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#define SDW_SHIM_IOCTL_DIBD BIT(9)
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#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
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#define SDW_SHIM_CTMCTL_DODS BIT(1)
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#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
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#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
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#define SDW_SHIM_WAKESTS_STATUS BIT(0)
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/* Intel ALH Register definitions */
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#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
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#define SDW_ALH_NUM_STREAMS 64
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#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
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#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
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#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
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#define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
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enum intel_pdi_type {
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INTEL_PDI_IN = 0,
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INTEL_PDI_OUT = 1,
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INTEL_PDI_BD = 2,
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};
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struct sdw_intel {
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struct sdw_cdns cdns;
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int instance;
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struct sdw_intel_link_res *link_res;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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#endif
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};
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#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
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/*
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* Read, write helpers for HW registers
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*/
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static inline int intel_readl(void __iomem *base, int offset)
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{
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return readl(base + offset);
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}
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static inline void intel_writel(void __iomem *base, int offset, int value)
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{
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writel(value, base + offset);
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}
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static inline u16 intel_readw(void __iomem *base, int offset)
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{
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return readw(base + offset);
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}
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static inline void intel_writew(void __iomem *base, int offset, u16 value)
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{
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writew(value, base + offset);
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}
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static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
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{
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int timeout = 10;
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u32 reg_read;
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writel(value, base + offset);
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do {
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reg_read = readl(base + offset);
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if (!(reg_read & mask))
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return 0;
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timeout--;
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udelay(50);
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} while (timeout != 0);
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return -EAGAIN;
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}
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static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
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{
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int timeout = 10;
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u32 reg_read;
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writel(value, base + offset);
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do {
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reg_read = readl(base + offset);
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if (reg_read & mask)
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return 0;
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timeout--;
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udelay(50);
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} while (timeout != 0);
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return -EAGAIN;
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}
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/*
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* debugfs
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*/
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#ifdef CONFIG_DEBUG_FS
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#define RD_BUF (2 * PAGE_SIZE)
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static ssize_t intel_sprintf(void __iomem *mem, bool l,
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char *buf, size_t pos, unsigned int reg)
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{
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int value;
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if (l)
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value = intel_readl(mem, reg);
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else
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value = intel_readw(mem, reg);
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return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
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}
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static int intel_reg_show(struct seq_file *s_file, void *data)
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{
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struct sdw_intel *sdw = s_file->private;
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void __iomem *s = sdw->link_res->shim;
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void __iomem *a = sdw->link_res->alh;
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char *buf;
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ssize_t ret;
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int i, j;
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unsigned int links, reg;
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buf = kzalloc(RD_BUF, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
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ret = scnprintf(buf, RD_BUF, "Register Value\n");
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ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
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for (i = 0; i < links; i++) {
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reg = SDW_SHIM_LCAP + i * 4;
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ret += intel_sprintf(s, true, buf, ret, reg);
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}
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for (i = 0; i < links; i++) {
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ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
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ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
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/*
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* the value 10 is the number of PDIs. We will need a
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* cleanup to remove hard-coded Intel configurations
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* from cadence_master.c
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*/
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for (j = 0; j < 10; j++) {
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ret += intel_sprintf(s, false, buf, ret,
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SDW_SHIM_PCMSYCHM(i, j));
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ret += intel_sprintf(s, false, buf, ret,
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SDW_SHIM_PCMSYCHC(i, j));
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}
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ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
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}
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ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
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ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
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ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
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for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
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ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
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seq_printf(s_file, "%s", buf);
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kfree(buf);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(intel_reg);
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static void intel_debugfs_init(struct sdw_intel *sdw)
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{
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struct dentry *root = sdw->cdns.bus.debugfs;
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if (!root)
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return;
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sdw->debugfs = debugfs_create_dir("intel-sdw", root);
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debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
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&intel_reg_fops);
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sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
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}
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static void intel_debugfs_exit(struct sdw_intel *sdw)
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{
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debugfs_remove_recursive(sdw->debugfs);
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}
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#else
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static void intel_debugfs_init(struct sdw_intel *sdw) {}
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static void intel_debugfs_exit(struct sdw_intel *sdw) {}
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#endif /* CONFIG_DEBUG_FS */
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/*
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* shim ops
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*/
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static int intel_link_power_up(struct sdw_intel *sdw)
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{
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unsigned int link_id = sdw->instance;
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void __iomem *shim = sdw->link_res->shim;
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int spa_mask, cpa_mask;
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int link_control, ret;
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/* Link power up sequence */
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link_control = intel_readl(shim, SDW_SHIM_LCTL);
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spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
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cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
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link_control |= spa_mask;
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ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
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if (ret < 0)
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return ret;
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sdw->cdns.link_up = true;
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return 0;
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}
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static int intel_shim_init(struct sdw_intel *sdw)
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{
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void __iomem *shim = sdw->link_res->shim;
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unsigned int link_id = sdw->instance;
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int sync_reg, ret;
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u16 ioctl = 0, act = 0;
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/* Initialize Shim */
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ioctl |= SDW_SHIM_IOCTL_BKE;
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl |= SDW_SHIM_IOCTL_WPDD;
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl |= SDW_SHIM_IOCTL_DO;
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl |= SDW_SHIM_IOCTL_DOE;
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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/* Switch to MIP from Glue logic */
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ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
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ioctl &= ~(SDW_SHIM_IOCTL_DOE);
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl &= ~(SDW_SHIM_IOCTL_DO);
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl |= (SDW_SHIM_IOCTL_MIF);
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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ioctl &= ~(SDW_SHIM_IOCTL_BKE);
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ioctl &= ~(SDW_SHIM_IOCTL_COE);
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intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
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act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
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act |= SDW_SHIM_CTMCTL_DACTQE;
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act |= SDW_SHIM_CTMCTL_DODS;
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intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
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/* Now set SyncPRD period */
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sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
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sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
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SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
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/* Set SyncCPU bit */
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sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
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ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
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SDW_SHIM_SYNC_SYNCCPU);
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if (ret < 0)
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dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
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return ret;
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}
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/*
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* PDI routines
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*/
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static void intel_pdi_init(struct sdw_intel *sdw,
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struct sdw_cdns_stream_config *config)
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{
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void __iomem *shim = sdw->link_res->shim;
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unsigned int link_id = sdw->instance;
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int pcm_cap, pdm_cap;
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/* PCM Stream Capability */
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pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
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config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
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config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
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SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
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config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
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dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
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config->pcm_bd, config->pcm_in, config->pcm_out);
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/* PDM Stream Capability */
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pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
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config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
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config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
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SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
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config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
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SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
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dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
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config->pdm_bd, config->pdm_in, config->pdm_out);
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}
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static int
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intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
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{
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void __iomem *shim = sdw->link_res->shim;
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unsigned int link_id = sdw->instance;
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int count;
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if (pcm) {
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count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
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/*
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* WORKAROUND: on all existing Intel controllers, pdi
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* number 2 reports channel count as 1 even though it
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* supports 8 channels. Performing hardcoding for pdi
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* number 2.
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*/
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if (pdi_num == 2)
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count = 7;
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} else {
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count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
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count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
|
|
SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
|
|
}
|
|
|
|
/* zero based values for channel count in register */
|
|
count++;
|
|
|
|
return count;
|
|
}
|
|
|
|
static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
|
|
struct sdw_cdns_pdi *pdi,
|
|
unsigned int num_pdi,
|
|
unsigned int *num_ch, bool pcm)
|
|
{
|
|
int i, ch_count = 0;
|
|
|
|
for (i = 0; i < num_pdi; i++) {
|
|
pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
|
|
ch_count += pdi->ch_count;
|
|
pdi++;
|
|
}
|
|
|
|
*num_ch = ch_count;
|
|
return 0;
|
|
}
|
|
|
|
static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
|
|
struct sdw_cdns_streams *stream, bool pcm)
|
|
{
|
|
intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
|
|
&stream->num_ch_bd, pcm);
|
|
|
|
intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
|
|
&stream->num_ch_in, pcm);
|
|
|
|
intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
|
|
&stream->num_ch_out, pcm);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_pdi_ch_update(struct sdw_intel *sdw)
|
|
{
|
|
/* First update PCM streams followed by PDM streams */
|
|
intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
|
|
intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
|
|
{
|
|
void __iomem *shim = sdw->link_res->shim;
|
|
unsigned int link_id = sdw->instance;
|
|
int pdi_conf = 0;
|
|
|
|
/* the Bulk and PCM streams are not contiguous */
|
|
pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
|
|
if (pdi->num >= 2)
|
|
pdi->intel_alh_id += 2;
|
|
|
|
/*
|
|
* Program stream parameters to stream SHIM register
|
|
* This is applicable for PCM stream only.
|
|
*/
|
|
if (pdi->type != SDW_STREAM_PCM)
|
|
return;
|
|
|
|
if (pdi->dir == SDW_DATA_DIR_RX)
|
|
pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
|
|
else
|
|
pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
|
|
|
|
pdi_conf |= (pdi->intel_alh_id <<
|
|
SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
|
|
pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
|
|
pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
|
|
|
|
intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
|
|
}
|
|
|
|
static void
|
|
intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
|
|
{
|
|
void __iomem *alh = sdw->link_res->alh;
|
|
unsigned int link_id = sdw->instance;
|
|
unsigned int conf;
|
|
|
|
/* the Bulk and PCM streams are not contiguous */
|
|
pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
|
|
if (pdi->num >= 2)
|
|
pdi->intel_alh_id += 2;
|
|
|
|
/* Program Stream config ALH register */
|
|
conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
|
|
|
|
conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
|
|
SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
|
|
|
|
conf |= ((pdi->ch_count - 1) <<
|
|
SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
|
|
|
|
intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
|
|
}
|
|
|
|
static int intel_params_stream(struct sdw_intel *sdw,
|
|
struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai,
|
|
struct snd_pcm_hw_params *hw_params,
|
|
int link_id, int alh_stream_id)
|
|
{
|
|
struct sdw_intel_link_res *res = sdw->link_res;
|
|
struct sdw_intel_stream_params_data params_data;
|
|
|
|
params_data.substream = substream;
|
|
params_data.dai = dai;
|
|
params_data.hw_params = hw_params;
|
|
params_data.link_id = link_id;
|
|
params_data.alh_stream_id = alh_stream_id;
|
|
|
|
if (res->ops && res->ops->params_stream && res->dev)
|
|
return res->ops->params_stream(res->dev,
|
|
¶ms_data);
|
|
return -EIO;
|
|
}
|
|
|
|
static int intel_free_stream(struct sdw_intel *sdw,
|
|
struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai,
|
|
int link_id)
|
|
{
|
|
struct sdw_intel_link_res *res = sdw->link_res;
|
|
struct sdw_intel_stream_free_data free_data;
|
|
|
|
free_data.substream = substream;
|
|
free_data.dai = dai;
|
|
free_data.link_id = link_id;
|
|
|
|
if (res->ops && res->ops->free_stream && res->dev)
|
|
return res->ops->free_stream(res->dev,
|
|
&free_data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* bank switch routines
|
|
*/
|
|
|
|
static int intel_pre_bank_switch(struct sdw_bus *bus)
|
|
{
|
|
struct sdw_cdns *cdns = bus_to_cdns(bus);
|
|
struct sdw_intel *sdw = cdns_to_intel(cdns);
|
|
void __iomem *shim = sdw->link_res->shim;
|
|
int sync_reg;
|
|
|
|
/* Write to register only for multi-link */
|
|
if (!bus->multi_link)
|
|
return 0;
|
|
|
|
/* Read SYNC register */
|
|
sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
|
|
sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
|
|
intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_post_bank_switch(struct sdw_bus *bus)
|
|
{
|
|
struct sdw_cdns *cdns = bus_to_cdns(bus);
|
|
struct sdw_intel *sdw = cdns_to_intel(cdns);
|
|
void __iomem *shim = sdw->link_res->shim;
|
|
int sync_reg, ret;
|
|
|
|
/* Write to register only for multi-link */
|
|
if (!bus->multi_link)
|
|
return 0;
|
|
|
|
/* Read SYNC register */
|
|
sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
|
|
|
|
/*
|
|
* post_bank_switch() ops is called from the bus in loop for
|
|
* all the Masters in the steam with the expectation that
|
|
* we trigger the bankswitch for the only first Master in the list
|
|
* and do nothing for the other Masters
|
|
*
|
|
* So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
|
|
*/
|
|
if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
|
|
return 0;
|
|
|
|
/*
|
|
* Set SyncGO bit to synchronously trigger a bank switch for
|
|
* all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
|
|
* the Masters.
|
|
*/
|
|
sync_reg |= SDW_SHIM_SYNC_SYNCGO;
|
|
|
|
ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
|
|
SDW_SHIM_SYNC_SYNCGO);
|
|
if (ret < 0)
|
|
dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* DAI routines
|
|
*/
|
|
|
|
static int sdw_stream_setup(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
|
struct sdw_stream_runtime *sdw_stream = NULL;
|
|
char *name;
|
|
int i, ret;
|
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
name = kasprintf(GFP_KERNEL, "%s-Playback", dai->name);
|
|
else
|
|
name = kasprintf(GFP_KERNEL, "%s-Capture", dai->name);
|
|
|
|
if (!name)
|
|
return -ENOMEM;
|
|
|
|
sdw_stream = sdw_alloc_stream(name);
|
|
if (!sdw_stream) {
|
|
dev_err(dai->dev, "alloc stream failed for DAI %s", dai->name);
|
|
ret = -ENOMEM;
|
|
goto error;
|
|
}
|
|
|
|
/* Set stream pointer on CPU DAI */
|
|
ret = snd_soc_dai_set_sdw_stream(dai, sdw_stream, substream->stream);
|
|
if (ret < 0) {
|
|
dev_err(dai->dev, "failed to set stream pointer on cpu dai %s",
|
|
dai->name);
|
|
goto release_stream;
|
|
}
|
|
|
|
/* Set stream pointer on all CODEC DAIs */
|
|
for (i = 0; i < rtd->num_codecs; i++) {
|
|
ret = snd_soc_dai_set_sdw_stream(asoc_rtd_to_codec(rtd, i), sdw_stream,
|
|
substream->stream);
|
|
if (ret < 0) {
|
|
dev_err(dai->dev, "failed to set stream pointer on codec dai %s",
|
|
asoc_rtd_to_codec(rtd, i)->name);
|
|
goto release_stream;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
release_stream:
|
|
sdw_release_stream(sdw_stream);
|
|
error:
|
|
kfree(name);
|
|
return ret;
|
|
}
|
|
|
|
static int intel_startup(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
/*
|
|
* TODO: add pm_runtime support here, the startup callback
|
|
* will make sure the IP is 'active'
|
|
*/
|
|
|
|
return sdw_stream_setup(substream, dai);
|
|
}
|
|
|
|
static int intel_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
|
|
struct sdw_intel *sdw = cdns_to_intel(cdns);
|
|
struct sdw_cdns_dma_data *dma;
|
|
struct sdw_cdns_pdi *pdi;
|
|
struct sdw_stream_config sconfig;
|
|
struct sdw_port_config *pconfig;
|
|
int ch, dir;
|
|
int ret;
|
|
bool pcm = true;
|
|
|
|
dma = snd_soc_dai_get_dma_data(dai, substream);
|
|
if (!dma)
|
|
return -EIO;
|
|
|
|
ch = params_channels(params);
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
|
|
dir = SDW_DATA_DIR_RX;
|
|
else
|
|
dir = SDW_DATA_DIR_TX;
|
|
|
|
if (dma->stream_type == SDW_STREAM_PDM)
|
|
pcm = false;
|
|
|
|
if (pcm)
|
|
pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
|
|
else
|
|
pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
|
|
|
|
if (!pdi) {
|
|
ret = -EINVAL;
|
|
goto error;
|
|
}
|
|
|
|
/* do run-time configurations for SHIM, ALH and PDI/PORT */
|
|
intel_pdi_shim_configure(sdw, pdi);
|
|
intel_pdi_alh_configure(sdw, pdi);
|
|
sdw_cdns_config_stream(cdns, ch, dir, pdi);
|
|
|
|
|
|
/* Inform DSP about PDI stream number */
|
|
ret = intel_params_stream(sdw, substream, dai, params,
|
|
sdw->instance,
|
|
pdi->intel_alh_id);
|
|
if (ret)
|
|
goto error;
|
|
|
|
sconfig.direction = dir;
|
|
sconfig.ch_count = ch;
|
|
sconfig.frame_rate = params_rate(params);
|
|
sconfig.type = dma->stream_type;
|
|
|
|
if (dma->stream_type == SDW_STREAM_PDM) {
|
|
sconfig.frame_rate *= 50;
|
|
sconfig.bps = 1;
|
|
} else {
|
|
sconfig.bps = snd_pcm_format_width(params_format(params));
|
|
}
|
|
|
|
/* Port configuration */
|
|
pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL);
|
|
if (!pconfig) {
|
|
ret = -ENOMEM;
|
|
goto error;
|
|
}
|
|
|
|
pconfig->num = pdi->num;
|
|
pconfig->ch_mask = (1 << ch) - 1;
|
|
|
|
ret = sdw_stream_add_master(&cdns->bus, &sconfig,
|
|
pconfig, 1, dma->stream);
|
|
if (ret)
|
|
dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
|
|
|
|
kfree(pconfig);
|
|
error:
|
|
return ret;
|
|
}
|
|
|
|
static int intel_prepare(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct sdw_cdns_dma_data *dma;
|
|
|
|
dma = snd_soc_dai_get_dma_data(dai, substream);
|
|
if (!dma) {
|
|
dev_err(dai->dev, "failed to get dma data in %s",
|
|
__func__);
|
|
return -EIO;
|
|
}
|
|
|
|
return sdw_prepare_stream(dma->stream);
|
|
}
|
|
|
|
static int intel_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct sdw_cdns_dma_data *dma;
|
|
int ret;
|
|
|
|
dma = snd_soc_dai_get_dma_data(dai, substream);
|
|
if (!dma) {
|
|
dev_err(dai->dev, "failed to get dma data in %s", __func__);
|
|
return -EIO;
|
|
}
|
|
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
ret = sdw_enable_stream(dma->stream);
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
ret = sdw_disable_stream(dma->stream);
|
|
break;
|
|
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
if (ret)
|
|
dev_err(dai->dev,
|
|
"%s trigger %d failed: %d",
|
|
__func__, cmd, ret);
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
|
|
{
|
|
struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
|
|
struct sdw_intel *sdw = cdns_to_intel(cdns);
|
|
struct sdw_cdns_dma_data *dma;
|
|
int ret;
|
|
|
|
dma = snd_soc_dai_get_dma_data(dai, substream);
|
|
if (!dma)
|
|
return -EIO;
|
|
|
|
ret = sdw_deprepare_stream(dma->stream);
|
|
if (ret) {
|
|
dev_err(dai->dev, "sdw_deprepare_stream: failed %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
|
|
if (ret < 0) {
|
|
dev_err(dai->dev, "remove master from stream %s failed: %d\n",
|
|
dma->stream->name, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = intel_free_stream(sdw, substream, dai, sdw->instance);
|
|
if (ret < 0) {
|
|
dev_err(dai->dev, "intel_free_stream: failed %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
kfree(dma->stream->name);
|
|
sdw_release_stream(dma->stream);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void intel_shutdown(struct snd_pcm_substream *substream,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct sdw_cdns_dma_data *dma;
|
|
|
|
dma = snd_soc_dai_get_dma_data(dai, substream);
|
|
if (!dma)
|
|
return;
|
|
|
|
snd_soc_dai_set_dma_data(dai, substream, NULL);
|
|
kfree(dma);
|
|
}
|
|
|
|
static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
|
|
void *stream, int direction)
|
|
{
|
|
return cdns_set_sdw_stream(dai, stream, true, direction);
|
|
}
|
|
|
|
static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
|
|
void *stream, int direction)
|
|
{
|
|
return cdns_set_sdw_stream(dai, stream, false, direction);
|
|
}
|
|
|
|
static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
|
|
.startup = intel_startup,
|
|
.hw_params = intel_hw_params,
|
|
.prepare = intel_prepare,
|
|
.trigger = intel_trigger,
|
|
.hw_free = intel_hw_free,
|
|
.shutdown = intel_shutdown,
|
|
.set_sdw_stream = intel_pcm_set_sdw_stream,
|
|
};
|
|
|
|
static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
|
|
.startup = intel_startup,
|
|
.hw_params = intel_hw_params,
|
|
.prepare = intel_prepare,
|
|
.trigger = intel_trigger,
|
|
.hw_free = intel_hw_free,
|
|
.shutdown = intel_shutdown,
|
|
.set_sdw_stream = intel_pdm_set_sdw_stream,
|
|
};
|
|
|
|
static const struct snd_soc_component_driver dai_component = {
|
|
.name = "soundwire",
|
|
};
|
|
|
|
static int intel_create_dai(struct sdw_cdns *cdns,
|
|
struct snd_soc_dai_driver *dais,
|
|
enum intel_pdi_type type,
|
|
u32 num, u32 off, u32 max_ch, bool pcm)
|
|
{
|
|
int i;
|
|
|
|
if (num == 0)
|
|
return 0;
|
|
|
|
/* TODO: Read supported rates/formats from hardware */
|
|
for (i = off; i < (off + num); i++) {
|
|
dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
|
|
cdns->instance, i);
|
|
if (!dais[i].name)
|
|
return -ENOMEM;
|
|
|
|
if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
|
|
dais[i].playback.channels_min = 1;
|
|
dais[i].playback.channels_max = max_ch;
|
|
dais[i].playback.rates = SNDRV_PCM_RATE_48000;
|
|
dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
|
|
}
|
|
|
|
if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
|
|
dais[i].capture.channels_min = 1;
|
|
dais[i].capture.channels_max = max_ch;
|
|
dais[i].capture.rates = SNDRV_PCM_RATE_48000;
|
|
dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
|
|
}
|
|
|
|
if (pcm)
|
|
dais[i].ops = &intel_pcm_dai_ops;
|
|
else
|
|
dais[i].ops = &intel_pdm_dai_ops;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_register_dai(struct sdw_intel *sdw)
|
|
{
|
|
struct sdw_cdns *cdns = &sdw->cdns;
|
|
struct sdw_cdns_streams *stream;
|
|
struct snd_soc_dai_driver *dais;
|
|
int num_dai, ret, off = 0;
|
|
|
|
/* DAIs are created based on total number of PDIs supported */
|
|
num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
|
|
|
|
dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
|
|
if (!dais)
|
|
return -ENOMEM;
|
|
|
|
/* Create PCM DAIs */
|
|
stream = &cdns->pcm;
|
|
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
|
|
off, stream->num_ch_in, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pcm.num_in;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
|
|
off, stream->num_ch_out, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pcm.num_out;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
|
|
off, stream->num_ch_bd, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Create PDM DAIs */
|
|
stream = &cdns->pdm;
|
|
off += cdns->pcm.num_bd;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
|
|
off, stream->num_ch_in, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pdm.num_in;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
|
|
off, stream->num_ch_out, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
off += cdns->pdm.num_out;
|
|
ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
|
|
off, stream->num_ch_bd, false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return snd_soc_register_component(cdns->dev, &dai_component,
|
|
dais, num_dai);
|
|
}
|
|
|
|
static int sdw_master_read_intel_prop(struct sdw_bus *bus)
|
|
{
|
|
struct sdw_master_prop *prop = &bus->prop;
|
|
struct fwnode_handle *link;
|
|
char name[32];
|
|
u32 quirk_mask;
|
|
|
|
/* Find master handle */
|
|
snprintf(name, sizeof(name),
|
|
"mipi-sdw-link-%d-subproperties", bus->link_id);
|
|
|
|
link = device_get_named_child_node(bus->dev, name);
|
|
if (!link) {
|
|
dev_err(bus->dev, "Master node %s not found\n", name);
|
|
return -EIO;
|
|
}
|
|
|
|
fwnode_property_read_u32(link,
|
|
"intel-sdw-ip-clock",
|
|
&prop->mclk_freq);
|
|
|
|
/* the values reported by BIOS are the 2x clock, not the bus clock */
|
|
prop->mclk_freq /= 2;
|
|
|
|
fwnode_property_read_u32(link,
|
|
"intel-quirk-mask",
|
|
&quirk_mask);
|
|
|
|
if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
|
|
prop->hw_disabled = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_prop_read(struct sdw_bus *bus)
|
|
{
|
|
/* Initialize with default handler to read all DisCo properties */
|
|
sdw_master_read_prop(bus);
|
|
|
|
/* read Intel-specific properties */
|
|
sdw_master_read_intel_prop(bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct sdw_master_ops sdw_intel_ops = {
|
|
.read_prop = sdw_master_read_prop,
|
|
.xfer_msg = cdns_xfer_msg,
|
|
.xfer_msg_defer = cdns_xfer_msg_defer,
|
|
.reset_page_addr = cdns_reset_page_addr,
|
|
.set_bus_conf = cdns_bus_conf,
|
|
.pre_bank_switch = intel_pre_bank_switch,
|
|
.post_bank_switch = intel_post_bank_switch,
|
|
};
|
|
|
|
static int intel_init(struct sdw_intel *sdw)
|
|
{
|
|
/* Initialize shim and controller */
|
|
intel_link_power_up(sdw);
|
|
intel_shim_init(sdw);
|
|
|
|
return sdw_cdns_init(&sdw->cdns);
|
|
}
|
|
|
|
/*
|
|
* probe and init
|
|
*/
|
|
static int intel_probe(struct platform_device *pdev)
|
|
{
|
|
struct sdw_cdns_stream_config config;
|
|
struct sdw_intel *sdw;
|
|
int ret;
|
|
|
|
sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
|
|
if (!sdw)
|
|
return -ENOMEM;
|
|
|
|
sdw->instance = pdev->id;
|
|
sdw->link_res = dev_get_platdata(&pdev->dev);
|
|
sdw->cdns.dev = &pdev->dev;
|
|
sdw->cdns.registers = sdw->link_res->registers;
|
|
sdw->cdns.instance = sdw->instance;
|
|
sdw->cdns.msg_count = 0;
|
|
sdw->cdns.bus.link_id = pdev->id;
|
|
|
|
sdw_cdns_probe(&sdw->cdns);
|
|
|
|
/* Set property read ops */
|
|
sdw_intel_ops.read_prop = intel_prop_read;
|
|
sdw->cdns.bus.ops = &sdw_intel_ops;
|
|
|
|
platform_set_drvdata(pdev, sdw);
|
|
|
|
ret = sdw_bus_master_add(&sdw->cdns.bus, &pdev->dev, pdev->dev.fwnode);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "sdw_bus_master_add fail: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
if (sdw->cdns.bus.prop.hw_disabled) {
|
|
dev_info(&pdev->dev, "SoundWire master %d is disabled, ignoring\n",
|
|
sdw->cdns.bus.link_id);
|
|
return 0;
|
|
}
|
|
|
|
/* Initialize shim, controller and Cadence IP */
|
|
ret = intel_init(sdw);
|
|
if (ret)
|
|
goto err_init;
|
|
|
|
/* Read the PDI config and initialize cadence PDI */
|
|
intel_pdi_init(sdw, &config);
|
|
ret = sdw_cdns_pdi_init(&sdw->cdns, config);
|
|
if (ret)
|
|
goto err_init;
|
|
|
|
intel_pdi_ch_update(sdw);
|
|
|
|
/* Acquire IRQ */
|
|
ret = request_threaded_irq(sdw->link_res->irq,
|
|
sdw_cdns_irq, sdw_cdns_thread,
|
|
IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
|
|
if (ret < 0) {
|
|
dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
|
|
sdw->link_res->irq);
|
|
goto err_init;
|
|
}
|
|
|
|
ret = sdw_cdns_enable_interrupt(&sdw->cdns, true);
|
|
if (ret < 0) {
|
|
dev_err(sdw->cdns.dev, "cannot enable interrupts\n");
|
|
goto err_init;
|
|
}
|
|
|
|
ret = sdw_cdns_exit_reset(&sdw->cdns);
|
|
if (ret < 0) {
|
|
dev_err(sdw->cdns.dev, "unable to exit bus reset sequence\n");
|
|
goto err_interrupt;
|
|
}
|
|
|
|
/* Register DAIs */
|
|
ret = intel_register_dai(sdw);
|
|
if (ret) {
|
|
dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
|
|
snd_soc_unregister_component(sdw->cdns.dev);
|
|
goto err_interrupt;
|
|
}
|
|
|
|
intel_debugfs_init(sdw);
|
|
|
|
return 0;
|
|
|
|
err_interrupt:
|
|
sdw_cdns_enable_interrupt(&sdw->cdns, false);
|
|
free_irq(sdw->link_res->irq, sdw);
|
|
err_init:
|
|
sdw_bus_master_delete(&sdw->cdns.bus);
|
|
return ret;
|
|
}
|
|
|
|
static int intel_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdw_intel *sdw;
|
|
|
|
sdw = platform_get_drvdata(pdev);
|
|
|
|
if (!sdw->cdns.bus.prop.hw_disabled) {
|
|
intel_debugfs_exit(sdw);
|
|
sdw_cdns_enable_interrupt(&sdw->cdns, false);
|
|
free_irq(sdw->link_res->irq, sdw);
|
|
snd_soc_unregister_component(sdw->cdns.dev);
|
|
}
|
|
sdw_bus_master_delete(&sdw->cdns.bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sdw_intel_drv = {
|
|
.probe = intel_probe,
|
|
.remove = intel_remove,
|
|
.driver = {
|
|
.name = "int-sdw",
|
|
|
|
},
|
|
};
|
|
|
|
module_platform_driver(sdw_intel_drv);
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
MODULE_ALIAS("platform:int-sdw");
|
|
MODULE_DESCRIPTION("Intel Soundwire Master Driver");
|