528 lines
14 KiB
C
528 lines
14 KiB
C
/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/cmd.h>
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#include <linux/mlx5/eswitch.h>
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#include <linux/module.h>
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#include "mlx5_core.h"
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#include "../../mlxfw/mlxfw.h"
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static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
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int outlen)
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{
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u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0};
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MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
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return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
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}
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int mlx5_query_board_id(struct mlx5_core_dev *dev)
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{
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u32 *out;
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int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
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int err;
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out = kzalloc(outlen, GFP_KERNEL);
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if (!out)
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return -ENOMEM;
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err = mlx5_cmd_query_adapter(dev, out, outlen);
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if (err)
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goto out;
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memcpy(dev->board_id,
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MLX5_ADDR_OF(query_adapter_out, out,
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query_adapter_struct.vsd_contd_psid),
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MLX5_FLD_SZ_BYTES(query_adapter_out,
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query_adapter_struct.vsd_contd_psid));
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out:
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kfree(out);
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return err;
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}
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int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
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{
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u32 *out;
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int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
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int err;
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out = kzalloc(outlen, GFP_KERNEL);
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if (!out)
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return -ENOMEM;
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err = mlx5_cmd_query_adapter(mdev, out, outlen);
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if (err)
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goto out;
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*vendor_id = MLX5_GET(query_adapter_out, out,
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query_adapter_struct.ieee_vendor_id);
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out:
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kfree(out);
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return err;
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}
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EXPORT_SYMBOL(mlx5_core_query_vendor_id);
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static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
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{
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return mlx5_query_pcam_reg(dev, dev->caps.pcam,
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MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
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MLX5_PCAM_REGS_5000_TO_507F);
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}
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static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
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{
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return mlx5_query_mcam_reg(dev, dev->caps.mcam,
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MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
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MLX5_MCAM_REGS_FIRST_128);
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}
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static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
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{
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return mlx5_query_qcam_reg(dev, dev->caps.qcam,
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MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
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MLX5_QCAM_REGS_FIRST_128);
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}
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int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
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{
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int err;
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err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
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if (err)
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return err;
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if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, pg)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, atomic)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, roce)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, nic_flow_table) ||
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MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, vport_group_manager) &&
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MLX5_ESWITCH_MANAGER(dev)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
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if (err)
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return err;
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}
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if (MLX5_ESWITCH_MANAGER(dev)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, vector_calc)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, qos)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
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if (err)
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return err;
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}
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if (MLX5_CAP_GEN(dev, debug))
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mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
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if (MLX5_CAP_GEN(dev, pcam_reg))
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mlx5_get_pcam_reg(dev);
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if (MLX5_CAP_GEN(dev, mcam_reg))
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mlx5_get_mcam_reg(dev);
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if (MLX5_CAP_GEN(dev, qcam_reg))
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mlx5_get_qcam_reg(dev);
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if (MLX5_CAP_GEN(dev, device_memory)) {
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err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_MEM);
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if (err)
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return err;
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}
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return 0;
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}
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int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
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{
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u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0};
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u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {0};
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int i;
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MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
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if (MLX5_CAP_GEN(dev, sw_owner_id)) {
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for (i = 0; i < 4; i++)
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MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
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sw_owner_id[i]);
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}
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return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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}
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int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
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{
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u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
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u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
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MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
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return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
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}
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int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
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{
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u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
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u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
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int force_state;
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int ret;
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if (!MLX5_CAP_GEN(dev, force_teardown)) {
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mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
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return -EOPNOTSUPP;
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}
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MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
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MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
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ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
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if (ret)
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return ret;
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force_state = MLX5_GET(teardown_hca_out, out, force_state);
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if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
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mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
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return -EIO;
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}
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return 0;
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}
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enum mlxsw_reg_mcc_instruction {
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MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
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MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
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MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
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MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
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MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
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MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
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};
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static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
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enum mlxsw_reg_mcc_instruction instr,
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u16 component_index, u32 update_handle,
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u32 component_size)
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{
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u32 out[MLX5_ST_SZ_DW(mcc_reg)];
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u32 in[MLX5_ST_SZ_DW(mcc_reg)];
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memset(in, 0, sizeof(in));
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MLX5_SET(mcc_reg, in, instruction, instr);
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MLX5_SET(mcc_reg, in, component_index, component_index);
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MLX5_SET(mcc_reg, in, update_handle, update_handle);
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MLX5_SET(mcc_reg, in, component_size, component_size);
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return mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_MCC, 0, 1);
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}
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static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
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u32 *update_handle, u8 *error_code,
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u8 *control_state)
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{
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u32 out[MLX5_ST_SZ_DW(mcc_reg)];
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u32 in[MLX5_ST_SZ_DW(mcc_reg)];
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int err;
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memset(in, 0, sizeof(in));
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memset(out, 0, sizeof(out));
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MLX5_SET(mcc_reg, in, update_handle, *update_handle);
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err = mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_MCC, 0, 0);
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if (err)
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goto out;
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*update_handle = MLX5_GET(mcc_reg, out, update_handle);
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*error_code = MLX5_GET(mcc_reg, out, error_code);
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*control_state = MLX5_GET(mcc_reg, out, control_state);
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out:
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return err;
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}
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static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
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u32 update_handle,
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u32 offset, u16 size,
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u8 *data)
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{
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int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
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u32 out[MLX5_ST_SZ_DW(mcda_reg)];
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int i, j, dw_size = size >> 2;
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__be32 data_element;
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u32 *in;
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in = kzalloc(in_size, GFP_KERNEL);
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if (!in)
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return -ENOMEM;
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MLX5_SET(mcda_reg, in, update_handle, update_handle);
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MLX5_SET(mcda_reg, in, offset, offset);
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MLX5_SET(mcda_reg, in, size, size);
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for (i = 0; i < dw_size; i++) {
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j = i * 4;
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data_element = htonl(*(u32 *)&data[j]);
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memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
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}
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err = mlx5_core_access_reg(dev, in, in_size, out,
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sizeof(out), MLX5_REG_MCDA, 0, 1);
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kfree(in);
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return err;
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}
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static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
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u16 component_index,
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u32 *max_component_size,
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u8 *log_mcda_word_size,
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u16 *mcda_max_write_size)
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{
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u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
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int offset = MLX5_ST_SZ_DW(mcqi_reg);
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u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
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int err;
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memset(in, 0, sizeof(in));
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memset(out, 0, sizeof(out));
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MLX5_SET(mcqi_reg, in, component_index, component_index);
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MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap));
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err = mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_MCQI, 0, 0);
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if (err)
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goto out;
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*max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size);
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*log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size);
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*mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size);
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out:
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return err;
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}
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struct mlx5_mlxfw_dev {
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struct mlxfw_dev mlxfw_dev;
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struct mlx5_core_dev *mlx5_core_dev;
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};
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static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
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u16 component_index, u32 *p_max_size,
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u8 *p_align_bits, u16 *p_max_write_size)
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{
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struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
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container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
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struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
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return mlx5_reg_mcqi_query(dev, component_index, p_max_size,
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p_align_bits, p_max_write_size);
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}
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static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
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{
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struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
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container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
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struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
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u8 control_state, error_code;
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int err;
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*fwhandle = 0;
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err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
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if (err)
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return err;
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if (control_state != MLXFW_FSM_STATE_IDLE)
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return -EBUSY;
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return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
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0, *fwhandle, 0);
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}
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static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
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u16 component_index, u32 component_size)
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{
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struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
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container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
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struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
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return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
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component_index, fwhandle, component_size);
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}
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static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
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u8 *data, u16 size, u32 offset)
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{
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struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
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container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
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struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
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return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
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}
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static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
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u16 component_index)
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{
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struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
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container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
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struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
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return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
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component_index, fwhandle, 0);
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}
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static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
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|
{
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struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
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container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
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struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
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|
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return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
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|
fwhandle, 0);
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}
|
|
|
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static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
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enum mlxfw_fsm_state *fsm_state,
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|
enum mlxfw_fsm_state_err *fsm_state_err)
|
|
{
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|
struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
|
|
container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
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|
struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
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u8 control_state, error_code;
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|
int err;
|
|
|
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err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
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|
if (err)
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|
return err;
|
|
|
|
*fsm_state = control_state;
|
|
*fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
|
|
MLXFW_FSM_STATE_ERR_MAX);
|
|
return 0;
|
|
}
|
|
|
|
static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
|
|
{
|
|
struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
|
|
container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
|
|
struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
|
|
|
|
mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
|
|
}
|
|
|
|
static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
|
|
{
|
|
struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
|
|
container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
|
|
struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
|
|
|
|
mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
|
|
fwhandle, 0);
|
|
}
|
|
|
|
static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
|
|
.component_query = mlx5_component_query,
|
|
.fsm_lock = mlx5_fsm_lock,
|
|
.fsm_component_update = mlx5_fsm_component_update,
|
|
.fsm_block_download = mlx5_fsm_block_download,
|
|
.fsm_component_verify = mlx5_fsm_component_verify,
|
|
.fsm_activate = mlx5_fsm_activate,
|
|
.fsm_query_state = mlx5_fsm_query_state,
|
|
.fsm_cancel = mlx5_fsm_cancel,
|
|
.fsm_release = mlx5_fsm_release
|
|
};
|
|
|
|
int mlx5_firmware_flash(struct mlx5_core_dev *dev,
|
|
const struct firmware *firmware)
|
|
{
|
|
struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
|
|
.mlxfw_dev = {
|
|
.ops = &mlx5_mlxfw_dev_ops,
|
|
.psid = dev->board_id,
|
|
.psid_size = strlen(dev->board_id),
|
|
},
|
|
.mlx5_core_dev = dev
|
|
};
|
|
|
|
if (!MLX5_CAP_GEN(dev, mcam_reg) ||
|
|
!MLX5_CAP_MCAM_REG(dev, mcqi) ||
|
|
!MLX5_CAP_MCAM_REG(dev, mcc) ||
|
|
!MLX5_CAP_MCAM_REG(dev, mcda)) {
|
|
pr_info("%s flashing isn't supported by the running FW\n", __func__);
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware);
|
|
}
|