cd871d517d
Since the Arria10's reset register offset is different from the Cyclone/Arria 5, it's best to add a new DT_MACHINE_START() for the Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: use altera_a10_dt_match for the A10 machine desc
54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
/*
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* Copyright 2012 Pavel Machek <pavel@denx.de>
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* Copyright (C) 2012-2015 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __MACH_CORE_H
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#define __MACH_CORE_H
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#define SOCFPGA_RSTMGR_CTRL 0x04
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#define SOCFPGA_RSTMGR_MODMPURST 0x10
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#define SOCFPGA_RSTMGR_MODPERRST 0x14
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#define SOCFPGA_RSTMGR_BRGMODRST 0x1c
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#define SOCFPGA_A10_RSTMGR_CTRL 0xC
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#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
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/* System Manager bits */
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#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
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#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
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#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
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extern void socfpga_init_clocks(void);
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extern void socfpga_sysmgr_init(void);
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extern void __iomem *sys_manager_base_addr;
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extern void __iomem *rst_manager_base_addr;
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extern void __iomem *sdr_ctl_base_addr;
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u32 socfpga_sdram_self_refresh(u32 sdr_base);
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extern unsigned int socfpga_sdram_self_refresh_sz;
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extern char secondary_trampoline, secondary_trampoline_end;
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extern unsigned long socfpga_cpu1start_addr;
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#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
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#endif
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