126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip VPU codec driver
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*
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* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
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*/
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#include <asm/unaligned.h>
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#include <media/v4l2-mem2mem.h>
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#include "rockchip_vpu_jpeg.h"
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#include "rockchip_vpu.h"
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#include "rockchip_vpu_v4l2.h"
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#include "rockchip_vpu_hw.h"
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#include "rk3288_vpu_regs.h"
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#define VEPU_JPEG_QUANT_TABLE_COUNT 16
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static void rk3288_vpu_set_src_img_ctrl(struct rockchip_vpu_dev *vpu,
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struct rockchip_vpu_ctx *ctx)
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{
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struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
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u32 reg;
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reg = VEPU_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width)
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| VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(0)
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| VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(0)
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| VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
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vepu_write_relaxed(vpu, reg, VEPU_REG_IN_IMG_CTRL);
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}
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static void rk3288_vpu_jpeg_enc_set_buffers(struct rockchip_vpu_dev *vpu,
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struct rockchip_vpu_ctx *ctx,
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struct vb2_buffer *src_buf)
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{
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struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
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dma_addr_t src[3];
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WARN_ON(pix_fmt->num_planes > 3);
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vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma,
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VEPU_REG_ADDR_OUTPUT_STREAM);
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vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size,
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VEPU_REG_STR_BUF_LIMIT);
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if (pix_fmt->num_planes == 1) {
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src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
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/* single plane formats we supported are all interlaced */
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vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
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} else if (pix_fmt->num_planes == 2) {
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src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
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src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
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vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
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vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);
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} else {
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src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
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src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
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src[2] = vb2_dma_contig_plane_dma_addr(src_buf, 2);
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vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
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vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);
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vepu_write_relaxed(vpu, src[2], VEPU_REG_ADDR_IN_PLANE_2);
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}
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}
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static void
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rk3288_vpu_jpeg_enc_set_qtable(struct rockchip_vpu_dev *vpu,
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unsigned char *luma_qtable,
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unsigned char *chroma_qtable)
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{
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u32 reg, i;
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for (i = 0; i < VEPU_JPEG_QUANT_TABLE_COUNT; i++) {
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reg = get_unaligned_be32(&luma_qtable[i]);
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vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_LUMA_QUAT(i));
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reg = get_unaligned_be32(&chroma_qtable[i]);
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vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_CHROMA_QUAT(i));
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}
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}
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void rk3288_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx)
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{
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struct rockchip_vpu_dev *vpu = ctx->dev;
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struct vb2_v4l2_buffer *src_buf, *dst_buf;
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struct rockchip_vpu_jpeg_ctx jpeg_ctx;
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u32 reg;
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src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
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dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
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memset(&jpeg_ctx, 0, sizeof(jpeg_ctx));
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jpeg_ctx.buffer = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
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jpeg_ctx.width = ctx->dst_fmt.width;
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jpeg_ctx.height = ctx->dst_fmt.height;
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jpeg_ctx.quality = ctx->jpeg_quality;
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rockchip_vpu_jpeg_header_assemble(&jpeg_ctx);
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/* Switch to JPEG encoder mode before writing registers */
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vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_JPEG,
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VEPU_REG_ENC_CTRL);
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rk3288_vpu_set_src_img_ctrl(vpu, ctx);
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rk3288_vpu_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);
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rk3288_vpu_jpeg_enc_set_qtable(vpu,
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rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 0),
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rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 1));
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reg = VEPU_REG_AXI_CTRL_OUTPUT_SWAP16
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| VEPU_REG_AXI_CTRL_INPUT_SWAP16
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| VEPU_REG_AXI_CTRL_BURST_LEN(16)
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| VEPU_REG_AXI_CTRL_OUTPUT_SWAP32
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| VEPU_REG_AXI_CTRL_INPUT_SWAP32
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| VEPU_REG_AXI_CTRL_OUTPUT_SWAP8
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| VEPU_REG_AXI_CTRL_INPUT_SWAP8;
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/* Make sure that all registers are written at this point. */
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vepu_write(vpu, reg, VEPU_REG_AXI_CTRL);
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reg = VEPU_REG_ENC_CTRL_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width))
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| VEPU_REG_ENC_CTRL_HEIGHT(JPEG_MB_HEIGHT(ctx->src_fmt.height))
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| VEPU_REG_ENC_CTRL_ENC_MODE_JPEG
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| VEPU_REG_ENC_PIC_INTRA
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| VEPU_REG_ENC_CTRL_EN_BIT;
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/* Kick the watchdog and start encoding */
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schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
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vepu_write(vpu, reg, VEPU_REG_ENC_CTRL);
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}
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