![Greg Kroah-Hartman](/assets/img/avatar_default.png)
* 'for-next/dwc3' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb: (392 commits) usb: dwc3: ep0: fix for possible early delayed_status usb: dwc3: gadget: fix stream enable bit usb: dwc3: ep0: fix GetStatus handling (again) usb: dwc3: ep0: use dwc3_request for ep0 requsts instead of usb_request usb: dwc3: use correct hwparam register for power mgm check usb: dwc3: omap: move to module_platform_driver usb: dwc3: workaround: missing disconnect event usb: dwc3: workaround: missing USB3 Reset event usb: dwc3: workaround: U1/U2 -> U0 transiton usb: dwc3: gadget: return early in dwc3_cleanup_done_reqs() usb: dwc3: ep0: handle delayed_status again usb: dwc3: ep0: push ep0state into xfernotready processing usb: dwc3: fix sparse errors usb: dwc3: fix few coding style problems usb: dwc3: move generic dwc3 code from gadget into core usb: dwc3: use a helper function for operation mode setting usb: dwc3: ep0: don't use ep0in for transfers usb: dwc3: ep0: use proper endianess in SetFeature for wIndex usb: dwc3: core: drop DWC3_EVENT_BUFFERS_MAX usb: dwc3: omap: add multiple instances support to OMAP ...
403 lines
11 KiB
C
403 lines
11 KiB
C
/**
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* dwc3-omap.c - OMAP Specific Glue layer
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/dwc3-omap.h>
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#include <linux/dma-mapping.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include "core.h"
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#include "io.h"
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/*
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* All these registers belong to OMAP's Wrapper around the
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* DesignWare USB3 Core.
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*/
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#define USBOTGSS_REVISION 0x0000
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#define USBOTGSS_SYSCONFIG 0x0010
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#define USBOTGSS_IRQ_EOI 0x0020
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#define USBOTGSS_IRQSTATUS_RAW_0 0x0024
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#define USBOTGSS_IRQSTATUS_0 0x0028
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#define USBOTGSS_IRQENABLE_SET_0 0x002c
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#define USBOTGSS_IRQENABLE_CLR_0 0x0030
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#define USBOTGSS_IRQSTATUS_RAW_1 0x0034
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#define USBOTGSS_IRQSTATUS_1 0x0038
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#define USBOTGSS_IRQENABLE_SET_1 0x003c
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#define USBOTGSS_IRQENABLE_CLR_1 0x0040
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#define USBOTGSS_UTMI_OTG_CTRL 0x0080
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#define USBOTGSS_UTMI_OTG_STATUS 0x0084
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#define USBOTGSS_MMRAM_OFFSET 0x0100
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#define USBOTGSS_FLADJ 0x0104
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#define USBOTGSS_DEBUG_CFG 0x0108
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#define USBOTGSS_DEBUG_DATA 0x010c
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/* SYSCONFIG REGISTER */
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#define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
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#define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
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#define USBOTGSS_STANDBYMODE_FORCE_STANDBY 0
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#define USBOTGSS_STANDBYMODE_NO_STANDBY 1
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#define USBOTGSS_STANDBYMODE_SMART_STANDBY 2
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#define USBOTGSS_STANDBYMODE_SMART_WAKEUP 3
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#define USBOTGSS_STANDBYMODE_MASK (0x03 << 4)
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#define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
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#define USBOTGSS_IDLEMODE_FORCE_IDLE 0
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#define USBOTGSS_IDLEMODE_NO_IDLE 1
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#define USBOTGSS_IDLEMODE_SMART_IDLE 2
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#define USBOTGSS_IDLEMODE_SMART_WAKEUP 3
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#define USBOTGSS_IDLEMODE_MASK (0x03 << 2)
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/* IRQ_EOI REGISTER */
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#define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
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/* IRQS0 BITS */
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#define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
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/* IRQ1 BITS */
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#define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
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#define USBOTGSS_IRQ1_OEVT (1 << 16)
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#define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
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#define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
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#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
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#define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
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#define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
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#define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
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#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
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#define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
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/* UTMI_OTG_CTRL REGISTER */
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#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
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#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
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#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
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#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
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/* UTMI_OTG_STATUS REGISTER */
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#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
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#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
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#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
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#define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
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#define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
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#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
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#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
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struct dwc3_omap {
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/* device lock */
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spinlock_t lock;
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struct platform_device *dwc3;
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struct device *dev;
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int irq;
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void __iomem *base;
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void *context;
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u32 resource_size;
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u32 dma_status:1;
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};
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static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
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{
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struct dwc3_omap *omap = _omap;
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u32 reg;
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spin_lock(&omap->lock);
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reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);
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if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
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dev_dbg(omap->dev, "DMA Disable was Cleared\n");
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omap->dma_status = false;
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}
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if (reg & USBOTGSS_IRQ1_OEVT)
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dev_dbg(omap->dev, "OTG Event\n");
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if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
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dev_dbg(omap->dev, "DRVVBUS Rise\n");
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if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
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dev_dbg(omap->dev, "CHRGVBUS Rise\n");
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if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
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dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
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if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
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dev_dbg(omap->dev, "IDPULLUP Rise\n");
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if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
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dev_dbg(omap->dev, "DRVVBUS Fall\n");
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if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
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dev_dbg(omap->dev, "CHRGVBUS Fall\n");
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if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
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dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
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if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
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dev_dbg(omap->dev, "IDPULLUP Fall\n");
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dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
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reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_0);
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dwc3_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
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spin_unlock(&omap->lock);
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return IRQ_HANDLED;
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}
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static int __devinit dwc3_omap_probe(struct platform_device *pdev)
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{
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struct dwc3_omap_data *pdata = pdev->dev.platform_data;
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struct platform_device *dwc3;
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struct dwc3_omap *omap;
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struct resource *res;
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int devid;
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int ret = -ENOMEM;
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int irq;
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u32 reg;
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void __iomem *base;
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void *context;
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omap = kzalloc(sizeof(*omap), GFP_KERNEL);
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if (!omap) {
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dev_err(&pdev->dev, "not enough memory\n");
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goto err0;
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}
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platform_set_drvdata(pdev, omap);
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irq = platform_get_irq(pdev, 1);
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if (irq < 0) {
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dev_err(&pdev->dev, "missing IRQ resource\n");
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ret = -EINVAL;
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goto err1;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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dev_err(&pdev->dev, "missing memory base resource\n");
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ret = -EINVAL;
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goto err1;
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}
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base = ioremap_nocache(res->start, resource_size(res));
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if (!base) {
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dev_err(&pdev->dev, "ioremap failed\n");
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goto err1;
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}
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devid = dwc3_get_device_id();
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if (devid < 0)
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goto err2;
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dwc3 = platform_device_alloc("dwc3", devid);
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if (!dwc3) {
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dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
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goto err3;
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}
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context = kzalloc(resource_size(res), GFP_KERNEL);
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if (!context) {
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dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n");
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goto err4;
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}
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spin_lock_init(&omap->lock);
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dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);
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dwc3->dev.parent = &pdev->dev;
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dwc3->dev.dma_mask = pdev->dev.dma_mask;
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dwc3->dev.dma_parms = pdev->dev.dma_parms;
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omap->resource_size = resource_size(res);
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omap->context = context;
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omap->dev = &pdev->dev;
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omap->irq = irq;
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omap->base = base;
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omap->dwc3 = dwc3;
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reg = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
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if (!pdata) {
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dev_dbg(&pdev->dev, "missing platform data\n");
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} else {
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switch (pdata->utmi_mode) {
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case DWC3_OMAP_UTMI_MODE_SW:
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reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
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break;
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case DWC3_OMAP_UTMI_MODE_HW:
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reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
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break;
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default:
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dev_dbg(&pdev->dev, "UNKNOWN utmi mode %d\n",
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pdata->utmi_mode);
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}
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}
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dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
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/* check the DMA Status */
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reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
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omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
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/* Set No-Idle and No-Standby */
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reg &= ~(USBOTGSS_STANDBYMODE_MASK
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| USBOTGSS_IDLEMODE_MASK);
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reg |= (USBOTGSS_SYSCONFIG_STANDBYMODE(USBOTGSS_STANDBYMODE_NO_STANDBY)
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| USBOTGSS_SYSCONFIG_IDLEMODE(USBOTGSS_IDLEMODE_NO_IDLE));
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dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
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ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,
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"dwc3-omap", omap);
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if (ret) {
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dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",
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omap->irq, ret);
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goto err5;
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}
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/* enable all IRQs */
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reg = USBOTGSS_IRQO_COREIRQ_ST;
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dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
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reg = (USBOTGSS_IRQ1_OEVT |
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USBOTGSS_IRQ1_DRVVBUS_RISE |
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USBOTGSS_IRQ1_CHRGVBUS_RISE |
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USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
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USBOTGSS_IRQ1_IDPULLUP_RISE |
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USBOTGSS_IRQ1_DRVVBUS_FALL |
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USBOTGSS_IRQ1_CHRGVBUS_FALL |
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USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
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USBOTGSS_IRQ1_IDPULLUP_FALL);
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dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
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ret = platform_device_add_resources(dwc3, pdev->resource,
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pdev->num_resources);
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if (ret) {
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dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
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goto err6;
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}
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ret = platform_device_add(dwc3);
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if (ret) {
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dev_err(&pdev->dev, "failed to register dwc3 device\n");
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goto err6;
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}
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return 0;
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err6:
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free_irq(omap->irq, omap);
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err5:
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kfree(omap->context);
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err4:
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platform_device_put(dwc3);
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err3:
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dwc3_put_device_id(devid);
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err2:
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iounmap(base);
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err1:
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kfree(omap);
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err0:
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return ret;
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}
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static int __devexit dwc3_omap_remove(struct platform_device *pdev)
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{
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struct dwc3_omap *omap = platform_get_drvdata(pdev);
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platform_device_unregister(omap->dwc3);
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dwc3_put_device_id(omap->dwc3->id);
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free_irq(omap->irq, omap);
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iounmap(omap->base);
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kfree(omap->context);
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kfree(omap);
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return 0;
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}
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static const struct of_device_id of_dwc3_matach[] = {
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{
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"ti,dwc3",
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, of_dwc3_matach);
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static struct platform_driver dwc3_omap_driver = {
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.probe = dwc3_omap_probe,
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.remove = __devexit_p(dwc3_omap_remove),
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.driver = {
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.name = "omap-dwc3",
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.of_match_table = of_dwc3_matach,
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},
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};
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module_platform_driver(dwc3_omap_driver);
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MODULE_ALIAS("platform:omap-dwc3");
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MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
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