![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
985 lines
22 KiB
C
985 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author: Jacob Chen <jacob-chen@iotwrt.com>
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*/
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/timer.h>
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#include <linux/platform_device.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-event.h>
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#include <media/v4l2-ioctl.h>
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#include <media/v4l2-mem2mem.h>
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#include <media/videobuf2-dma-sg.h>
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#include <media/videobuf2-v4l2.h>
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#include "rga-hw.h"
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#include "rga.h"
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static int debug;
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module_param(debug, int, 0644);
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static void device_run(void *prv)
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{
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struct rga_ctx *ctx = prv;
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struct rockchip_rga *rga = ctx->rga;
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struct vb2_v4l2_buffer *src, *dst;
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unsigned long flags;
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spin_lock_irqsave(&rga->ctrl_lock, flags);
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rga->curr = ctx;
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src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
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dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
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rga_buf_map(&src->vb2_buf);
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rga_buf_map(&dst->vb2_buf);
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rga_hw_start(rga);
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spin_unlock_irqrestore(&rga->ctrl_lock, flags);
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}
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static irqreturn_t rga_isr(int irq, void *prv)
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{
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struct rockchip_rga *rga = prv;
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int intr;
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intr = rga_read(rga, RGA_INT) & 0xf;
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rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
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if (intr & 0x04) {
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struct vb2_v4l2_buffer *src, *dst;
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struct rga_ctx *ctx = rga->curr;
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WARN_ON(!ctx);
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rga->curr = NULL;
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src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
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dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
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WARN_ON(!src);
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WARN_ON(!dst);
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dst->timecode = src->timecode;
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dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
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dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
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dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
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v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
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v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
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v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
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}
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return IRQ_HANDLED;
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}
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static const struct v4l2_m2m_ops rga_m2m_ops = {
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.device_run = device_run,
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};
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static int
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queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
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{
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struct rga_ctx *ctx = priv;
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int ret;
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src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
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src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
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src_vq->drv_priv = ctx;
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src_vq->ops = &rga_qops;
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src_vq->mem_ops = &vb2_dma_sg_memops;
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src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
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src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
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src_vq->lock = &ctx->rga->mutex;
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src_vq->dev = ctx->rga->v4l2_dev.dev;
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ret = vb2_queue_init(src_vq);
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if (ret)
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return ret;
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dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
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dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
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dst_vq->drv_priv = ctx;
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dst_vq->ops = &rga_qops;
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dst_vq->mem_ops = &vb2_dma_sg_memops;
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dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
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dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
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dst_vq->lock = &ctx->rga->mutex;
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dst_vq->dev = ctx->rga->v4l2_dev.dev;
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return vb2_queue_init(dst_vq);
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}
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static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
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{
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struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
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ctrl_handler);
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unsigned long flags;
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spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
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switch (ctrl->id) {
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case V4L2_CID_HFLIP:
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ctx->hflip = ctrl->val;
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break;
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case V4L2_CID_VFLIP:
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ctx->vflip = ctrl->val;
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break;
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case V4L2_CID_ROTATE:
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ctx->rotate = ctrl->val;
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break;
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case V4L2_CID_BG_COLOR:
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ctx->fill_color = ctrl->val;
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break;
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}
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spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
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return 0;
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}
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static const struct v4l2_ctrl_ops rga_ctrl_ops = {
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.s_ctrl = rga_s_ctrl,
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};
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static int rga_setup_ctrls(struct rga_ctx *ctx)
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{
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struct rockchip_rga *rga = ctx->rga;
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v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
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v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
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V4L2_CID_HFLIP, 0, 1, 1, 0);
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v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
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V4L2_CID_VFLIP, 0, 1, 1, 0);
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v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
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V4L2_CID_ROTATE, 0, 270, 90, 0);
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v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
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V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
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if (ctx->ctrl_handler.error) {
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int err = ctx->ctrl_handler.error;
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v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
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v4l2_ctrl_handler_free(&ctx->ctrl_handler);
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return err;
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}
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return 0;
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}
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static struct rga_fmt formats[] = {
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{
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.fourcc = V4L2_PIX_FMT_ARGB32,
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.color_swap = RGA_COLOR_RB_SWAP,
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.hw_format = RGA_COLOR_FMT_ABGR8888,
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.depth = 32,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_XRGB32,
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.color_swap = RGA_COLOR_RB_SWAP,
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.hw_format = RGA_COLOR_FMT_XBGR8888,
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.depth = 32,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_ABGR32,
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.color_swap = RGA_COLOR_ALPHA_SWAP,
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.hw_format = RGA_COLOR_FMT_ABGR8888,
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.depth = 32,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_XBGR32,
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.color_swap = RGA_COLOR_ALPHA_SWAP,
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.hw_format = RGA_COLOR_FMT_XBGR8888,
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.depth = 32,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_RGB24,
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.color_swap = RGA_COLOR_NONE_SWAP,
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.hw_format = RGA_COLOR_FMT_RGB888,
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.depth = 24,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_BGR24,
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.color_swap = RGA_COLOR_RB_SWAP,
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.hw_format = RGA_COLOR_FMT_RGB888,
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.depth = 24,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_ARGB444,
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.color_swap = RGA_COLOR_RB_SWAP,
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.hw_format = RGA_COLOR_FMT_ABGR4444,
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.depth = 16,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_ARGB555,
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.color_swap = RGA_COLOR_RB_SWAP,
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.hw_format = RGA_COLOR_FMT_ABGR1555,
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.depth = 16,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_RGB565,
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.color_swap = RGA_COLOR_RB_SWAP,
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.hw_format = RGA_COLOR_FMT_BGR565,
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.depth = 16,
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.uv_factor = 1,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_NV21,
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.color_swap = RGA_COLOR_UV_SWAP,
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.hw_format = RGA_COLOR_FMT_YUV420SP,
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.depth = 12,
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.uv_factor = 4,
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.y_div = 2,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_NV61,
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.color_swap = RGA_COLOR_UV_SWAP,
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.hw_format = RGA_COLOR_FMT_YUV422SP,
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.depth = 16,
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.uv_factor = 2,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_NV12,
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.color_swap = RGA_COLOR_NONE_SWAP,
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.hw_format = RGA_COLOR_FMT_YUV420SP,
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.depth = 12,
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.uv_factor = 4,
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.y_div = 2,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_NV16,
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.color_swap = RGA_COLOR_NONE_SWAP,
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.hw_format = RGA_COLOR_FMT_YUV422SP,
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.depth = 16,
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.uv_factor = 2,
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.y_div = 1,
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.x_div = 1,
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},
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{
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.fourcc = V4L2_PIX_FMT_YUV420,
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.color_swap = RGA_COLOR_NONE_SWAP,
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.hw_format = RGA_COLOR_FMT_YUV420P,
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.depth = 12,
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.uv_factor = 4,
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.y_div = 2,
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.x_div = 2,
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},
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{
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.fourcc = V4L2_PIX_FMT_YUV422P,
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.color_swap = RGA_COLOR_NONE_SWAP,
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.hw_format = RGA_COLOR_FMT_YUV422P,
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.depth = 16,
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.uv_factor = 2,
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.y_div = 1,
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.x_div = 2,
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},
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{
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.fourcc = V4L2_PIX_FMT_YVU420,
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.color_swap = RGA_COLOR_UV_SWAP,
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.hw_format = RGA_COLOR_FMT_YUV420P,
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.depth = 12,
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.uv_factor = 4,
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.y_div = 2,
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.x_div = 2,
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},
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};
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#define NUM_FORMATS ARRAY_SIZE(formats)
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static struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
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{
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unsigned int i;
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for (i = 0; i < NUM_FORMATS; i++) {
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if (formats[i].fourcc == f->fmt.pix.pixelformat)
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return &formats[i];
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}
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return NULL;
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}
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static struct rga_frame def_frame = {
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.width = DEFAULT_WIDTH,
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.height = DEFAULT_HEIGHT,
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.colorspace = V4L2_COLORSPACE_DEFAULT,
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.crop.left = 0,
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.crop.top = 0,
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.crop.width = DEFAULT_WIDTH,
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.crop.height = DEFAULT_HEIGHT,
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.fmt = &formats[0],
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};
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struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
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{
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switch (type) {
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case V4L2_BUF_TYPE_VIDEO_OUTPUT:
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return &ctx->in;
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case V4L2_BUF_TYPE_VIDEO_CAPTURE:
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return &ctx->out;
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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static int rga_open(struct file *file)
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{
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struct rockchip_rga *rga = video_drvdata(file);
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struct rga_ctx *ctx = NULL;
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int ret = 0;
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctx->rga = rga;
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/* Set default formats */
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ctx->in = def_frame;
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ctx->out = def_frame;
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if (mutex_lock_interruptible(&rga->mutex)) {
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kfree(ctx);
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return -ERESTARTSYS;
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}
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ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
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if (IS_ERR(ctx->fh.m2m_ctx)) {
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ret = PTR_ERR(ctx->fh.m2m_ctx);
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mutex_unlock(&rga->mutex);
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kfree(ctx);
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return ret;
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}
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v4l2_fh_init(&ctx->fh, video_devdata(file));
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file->private_data = &ctx->fh;
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v4l2_fh_add(&ctx->fh);
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rga_setup_ctrls(ctx);
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/* Write the default values to the ctx struct */
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v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
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ctx->fh.ctrl_handler = &ctx->ctrl_handler;
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mutex_unlock(&rga->mutex);
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return 0;
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}
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static int rga_release(struct file *file)
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{
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struct rga_ctx *ctx =
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container_of(file->private_data, struct rga_ctx, fh);
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struct rockchip_rga *rga = ctx->rga;
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mutex_lock(&rga->mutex);
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v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
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v4l2_ctrl_handler_free(&ctx->ctrl_handler);
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v4l2_fh_del(&ctx->fh);
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v4l2_fh_exit(&ctx->fh);
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kfree(ctx);
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mutex_unlock(&rga->mutex);
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return 0;
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}
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static const struct v4l2_file_operations rga_fops = {
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.owner = THIS_MODULE,
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.open = rga_open,
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.release = rga_release,
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.poll = v4l2_m2m_fop_poll,
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.unlocked_ioctl = video_ioctl2,
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.mmap = v4l2_m2m_fop_mmap,
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};
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static int
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vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
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{
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strscpy(cap->driver, RGA_NAME, sizeof(cap->driver));
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strscpy(cap->card, "rockchip-rga", sizeof(cap->card));
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strscpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
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return 0;
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}
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static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
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{
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struct rga_fmt *fmt;
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if (f->index >= NUM_FORMATS)
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return -EINVAL;
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fmt = &formats[f->index];
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f->pixelformat = fmt->fourcc;
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return 0;
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}
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static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
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{
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struct rga_ctx *ctx = prv;
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struct vb2_queue *vq;
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struct rga_frame *frm;
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vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
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if (!vq)
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return -EINVAL;
|
|
frm = rga_get_frame(ctx, f->type);
|
|
if (IS_ERR(frm))
|
|
return PTR_ERR(frm);
|
|
|
|
f->fmt.pix.width = frm->width;
|
|
f->fmt.pix.height = frm->height;
|
|
f->fmt.pix.field = V4L2_FIELD_NONE;
|
|
f->fmt.pix.pixelformat = frm->fmt->fourcc;
|
|
f->fmt.pix.bytesperline = frm->stride;
|
|
f->fmt.pix.sizeimage = frm->size;
|
|
f->fmt.pix.colorspace = frm->colorspace;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
|
|
{
|
|
struct rga_fmt *fmt;
|
|
|
|
fmt = rga_fmt_find(f);
|
|
if (!fmt) {
|
|
fmt = &formats[0];
|
|
f->fmt.pix.pixelformat = fmt->fourcc;
|
|
}
|
|
|
|
f->fmt.pix.field = V4L2_FIELD_NONE;
|
|
|
|
if (f->fmt.pix.width > MAX_WIDTH)
|
|
f->fmt.pix.width = MAX_WIDTH;
|
|
if (f->fmt.pix.height > MAX_HEIGHT)
|
|
f->fmt.pix.height = MAX_HEIGHT;
|
|
|
|
if (f->fmt.pix.width < MIN_WIDTH)
|
|
f->fmt.pix.width = MIN_WIDTH;
|
|
if (f->fmt.pix.height < MIN_HEIGHT)
|
|
f->fmt.pix.height = MIN_HEIGHT;
|
|
|
|
if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
|
|
f->fmt.pix.bytesperline = f->fmt.pix.width;
|
|
else
|
|
f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
|
|
|
|
f->fmt.pix.sizeimage =
|
|
f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
|
|
{
|
|
struct rga_ctx *ctx = prv;
|
|
struct rockchip_rga *rga = ctx->rga;
|
|
struct vb2_queue *vq;
|
|
struct rga_frame *frm;
|
|
struct rga_fmt *fmt;
|
|
int ret = 0;
|
|
|
|
/* Adjust all values accordingly to the hardware capabilities
|
|
* and chosen format.
|
|
*/
|
|
ret = vidioc_try_fmt(file, prv, f);
|
|
if (ret)
|
|
return ret;
|
|
vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
|
|
if (vb2_is_busy(vq)) {
|
|
v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
|
|
return -EBUSY;
|
|
}
|
|
frm = rga_get_frame(ctx, f->type);
|
|
if (IS_ERR(frm))
|
|
return PTR_ERR(frm);
|
|
fmt = rga_fmt_find(f);
|
|
if (!fmt)
|
|
return -EINVAL;
|
|
frm->width = f->fmt.pix.width;
|
|
frm->height = f->fmt.pix.height;
|
|
frm->size = f->fmt.pix.sizeimage;
|
|
frm->fmt = fmt;
|
|
frm->stride = f->fmt.pix.bytesperline;
|
|
frm->colorspace = f->fmt.pix.colorspace;
|
|
|
|
/* Reset crop settings */
|
|
frm->crop.left = 0;
|
|
frm->crop.top = 0;
|
|
frm->crop.width = frm->width;
|
|
frm->crop.height = frm->height;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vidioc_g_selection(struct file *file, void *prv,
|
|
struct v4l2_selection *s)
|
|
{
|
|
struct rga_ctx *ctx = prv;
|
|
struct rga_frame *f;
|
|
bool use_frame = false;
|
|
|
|
f = rga_get_frame(ctx, s->type);
|
|
if (IS_ERR(f))
|
|
return PTR_ERR(f);
|
|
|
|
switch (s->target) {
|
|
case V4L2_SEL_TGT_COMPOSE_DEFAULT:
|
|
case V4L2_SEL_TGT_COMPOSE_BOUNDS:
|
|
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
|
|
return -EINVAL;
|
|
break;
|
|
case V4L2_SEL_TGT_CROP_DEFAULT:
|
|
case V4L2_SEL_TGT_CROP_BOUNDS:
|
|
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
|
|
return -EINVAL;
|
|
break;
|
|
case V4L2_SEL_TGT_COMPOSE:
|
|
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
|
|
return -EINVAL;
|
|
use_frame = true;
|
|
break;
|
|
case V4L2_SEL_TGT_CROP:
|
|
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
|
|
return -EINVAL;
|
|
use_frame = true;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (use_frame) {
|
|
s->r = f->crop;
|
|
} else {
|
|
s->r.left = 0;
|
|
s->r.top = 0;
|
|
s->r.width = f->width;
|
|
s->r.height = f->height;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vidioc_s_selection(struct file *file, void *prv,
|
|
struct v4l2_selection *s)
|
|
{
|
|
struct rga_ctx *ctx = prv;
|
|
struct rockchip_rga *rga = ctx->rga;
|
|
struct rga_frame *f;
|
|
int ret = 0;
|
|
|
|
f = rga_get_frame(ctx, s->type);
|
|
if (IS_ERR(f))
|
|
return PTR_ERR(f);
|
|
|
|
switch (s->target) {
|
|
case V4L2_SEL_TGT_COMPOSE:
|
|
/*
|
|
* COMPOSE target is only valid for capture buffer type, return
|
|
* error for output buffer type
|
|
*/
|
|
if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
|
|
return -EINVAL;
|
|
break;
|
|
case V4L2_SEL_TGT_CROP:
|
|
/*
|
|
* CROP target is only valid for output buffer type, return
|
|
* error for capture buffer type
|
|
*/
|
|
if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
|
|
return -EINVAL;
|
|
break;
|
|
/*
|
|
* bound and default crop/compose targets are invalid targets to
|
|
* try/set
|
|
*/
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (s->r.top < 0 || s->r.left < 0) {
|
|
v4l2_dbg(debug, 1, &rga->v4l2_dev,
|
|
"doesn't support negative values for top & left.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (s->r.left + s->r.width > f->width ||
|
|
s->r.top + s->r.height > f->height ||
|
|
s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
|
|
v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
f->crop = s->r;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct v4l2_ioctl_ops rga_ioctl_ops = {
|
|
.vidioc_querycap = vidioc_querycap,
|
|
|
|
.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
|
|
.vidioc_g_fmt_vid_cap = vidioc_g_fmt,
|
|
.vidioc_try_fmt_vid_cap = vidioc_try_fmt,
|
|
.vidioc_s_fmt_vid_cap = vidioc_s_fmt,
|
|
|
|
.vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
|
|
.vidioc_g_fmt_vid_out = vidioc_g_fmt,
|
|
.vidioc_try_fmt_vid_out = vidioc_try_fmt,
|
|
.vidioc_s_fmt_vid_out = vidioc_s_fmt,
|
|
|
|
.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
|
|
.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
|
|
.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
|
|
.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
|
|
.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
|
|
.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
|
|
.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
|
|
|
|
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
|
|
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
|
|
|
|
.vidioc_streamon = v4l2_m2m_ioctl_streamon,
|
|
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
|
|
|
|
.vidioc_g_selection = vidioc_g_selection,
|
|
.vidioc_s_selection = vidioc_s_selection,
|
|
};
|
|
|
|
static const struct video_device rga_videodev = {
|
|
.name = "rockchip-rga",
|
|
.fops = &rga_fops,
|
|
.ioctl_ops = &rga_ioctl_ops,
|
|
.minor = -1,
|
|
.release = video_device_release,
|
|
.vfl_dir = VFL_DIR_M2M,
|
|
.device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
|
|
};
|
|
|
|
static int rga_enable_clocks(struct rockchip_rga *rga)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(rga->sclk);
|
|
if (ret) {
|
|
dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_prepare_enable(rga->aclk);
|
|
if (ret) {
|
|
dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
|
|
goto err_disable_sclk;
|
|
}
|
|
|
|
ret = clk_prepare_enable(rga->hclk);
|
|
if (ret) {
|
|
dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
|
|
goto err_disable_aclk;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_disable_sclk:
|
|
clk_disable_unprepare(rga->sclk);
|
|
err_disable_aclk:
|
|
clk_disable_unprepare(rga->aclk);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void rga_disable_clocks(struct rockchip_rga *rga)
|
|
{
|
|
clk_disable_unprepare(rga->sclk);
|
|
clk_disable_unprepare(rga->hclk);
|
|
clk_disable_unprepare(rga->aclk);
|
|
}
|
|
|
|
static int rga_parse_dt(struct rockchip_rga *rga)
|
|
{
|
|
struct reset_control *core_rst, *axi_rst, *ahb_rst;
|
|
|
|
core_rst = devm_reset_control_get(rga->dev, "core");
|
|
if (IS_ERR(core_rst)) {
|
|
dev_err(rga->dev, "failed to get core reset controller\n");
|
|
return PTR_ERR(core_rst);
|
|
}
|
|
|
|
axi_rst = devm_reset_control_get(rga->dev, "axi");
|
|
if (IS_ERR(axi_rst)) {
|
|
dev_err(rga->dev, "failed to get axi reset controller\n");
|
|
return PTR_ERR(axi_rst);
|
|
}
|
|
|
|
ahb_rst = devm_reset_control_get(rga->dev, "ahb");
|
|
if (IS_ERR(ahb_rst)) {
|
|
dev_err(rga->dev, "failed to get ahb reset controller\n");
|
|
return PTR_ERR(ahb_rst);
|
|
}
|
|
|
|
reset_control_assert(core_rst);
|
|
udelay(1);
|
|
reset_control_deassert(core_rst);
|
|
|
|
reset_control_assert(axi_rst);
|
|
udelay(1);
|
|
reset_control_deassert(axi_rst);
|
|
|
|
reset_control_assert(ahb_rst);
|
|
udelay(1);
|
|
reset_control_deassert(ahb_rst);
|
|
|
|
rga->sclk = devm_clk_get(rga->dev, "sclk");
|
|
if (IS_ERR(rga->sclk)) {
|
|
dev_err(rga->dev, "failed to get sclk clock\n");
|
|
return PTR_ERR(rga->sclk);
|
|
}
|
|
|
|
rga->aclk = devm_clk_get(rga->dev, "aclk");
|
|
if (IS_ERR(rga->aclk)) {
|
|
dev_err(rga->dev, "failed to get aclk clock\n");
|
|
return PTR_ERR(rga->aclk);
|
|
}
|
|
|
|
rga->hclk = devm_clk_get(rga->dev, "hclk");
|
|
if (IS_ERR(rga->hclk)) {
|
|
dev_err(rga->dev, "failed to get hclk clock\n");
|
|
return PTR_ERR(rga->hclk);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rga_probe(struct platform_device *pdev)
|
|
{
|
|
struct rockchip_rga *rga;
|
|
struct video_device *vfd;
|
|
struct resource *res;
|
|
int ret = 0;
|
|
int irq;
|
|
|
|
if (!pdev->dev.of_node)
|
|
return -ENODEV;
|
|
|
|
rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
|
|
if (!rga)
|
|
return -ENOMEM;
|
|
|
|
rga->dev = &pdev->dev;
|
|
spin_lock_init(&rga->ctrl_lock);
|
|
mutex_init(&rga->mutex);
|
|
|
|
ret = rga_parse_dt(rga);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "Unable to parse OF data\n");
|
|
|
|
pm_runtime_enable(rga->dev);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
rga->regs = devm_ioremap_resource(rga->dev, res);
|
|
if (IS_ERR(rga->regs)) {
|
|
ret = PTR_ERR(rga->regs);
|
|
goto err_put_clk;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(rga->dev, "failed to get irq\n");
|
|
ret = irq;
|
|
goto err_put_clk;
|
|
}
|
|
|
|
ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
|
|
dev_name(rga->dev), rga);
|
|
if (ret < 0) {
|
|
dev_err(rga->dev, "failed to request irq\n");
|
|
goto err_put_clk;
|
|
}
|
|
|
|
ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
|
|
if (ret)
|
|
goto err_put_clk;
|
|
vfd = video_device_alloc();
|
|
if (!vfd) {
|
|
v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
|
|
ret = -ENOMEM;
|
|
goto unreg_v4l2_dev;
|
|
}
|
|
*vfd = rga_videodev;
|
|
vfd->lock = &rga->mutex;
|
|
vfd->v4l2_dev = &rga->v4l2_dev;
|
|
|
|
video_set_drvdata(vfd, rga);
|
|
rga->vfd = vfd;
|
|
|
|
platform_set_drvdata(pdev, rga);
|
|
rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
|
|
if (IS_ERR(rga->m2m_dev)) {
|
|
v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
|
|
ret = PTR_ERR(rga->m2m_dev);
|
|
goto unreg_video_dev;
|
|
}
|
|
|
|
pm_runtime_get_sync(rga->dev);
|
|
|
|
rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
|
|
rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
|
|
|
|
v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
|
|
rga->version.major, rga->version.minor);
|
|
|
|
pm_runtime_put(rga->dev);
|
|
|
|
/* Create CMD buffer */
|
|
rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
|
|
&rga->cmdbuf_phy, GFP_KERNEL,
|
|
DMA_ATTR_WRITE_COMBINE);
|
|
|
|
rga->src_mmu_pages =
|
|
(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
|
|
rga->dst_mmu_pages =
|
|
(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
|
|
|
|
def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
|
|
def_frame.size = def_frame.stride * def_frame.height;
|
|
|
|
ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
|
|
if (ret) {
|
|
v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
|
|
goto rel_vdev;
|
|
}
|
|
|
|
v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
|
|
vfd->name, video_device_node_name(vfd));
|
|
|
|
return 0;
|
|
|
|
rel_vdev:
|
|
video_device_release(vfd);
|
|
unreg_video_dev:
|
|
video_unregister_device(rga->vfd);
|
|
unreg_v4l2_dev:
|
|
v4l2_device_unregister(&rga->v4l2_dev);
|
|
err_put_clk:
|
|
pm_runtime_disable(rga->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rga_remove(struct platform_device *pdev)
|
|
{
|
|
struct rockchip_rga *rga = platform_get_drvdata(pdev);
|
|
|
|
dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
|
|
rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
|
|
|
|
free_pages((unsigned long)rga->src_mmu_pages, 3);
|
|
free_pages((unsigned long)rga->dst_mmu_pages, 3);
|
|
|
|
v4l2_info(&rga->v4l2_dev, "Removing\n");
|
|
|
|
v4l2_m2m_release(rga->m2m_dev);
|
|
video_unregister_device(rga->vfd);
|
|
v4l2_device_unregister(&rga->v4l2_dev);
|
|
|
|
pm_runtime_disable(rga->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused rga_runtime_suspend(struct device *dev)
|
|
{
|
|
struct rockchip_rga *rga = dev_get_drvdata(dev);
|
|
|
|
rga_disable_clocks(rga);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused rga_runtime_resume(struct device *dev)
|
|
{
|
|
struct rockchip_rga *rga = dev_get_drvdata(dev);
|
|
|
|
return rga_enable_clocks(rga);
|
|
}
|
|
|
|
static const struct dev_pm_ops rga_pm = {
|
|
SET_RUNTIME_PM_OPS(rga_runtime_suspend,
|
|
rga_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct of_device_id rockchip_rga_match[] = {
|
|
{
|
|
.compatible = "rockchip,rk3288-rga",
|
|
},
|
|
{
|
|
.compatible = "rockchip,rk3399-rga",
|
|
},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, rockchip_rga_match);
|
|
|
|
static struct platform_driver rga_pdrv = {
|
|
.probe = rga_probe,
|
|
.remove = rga_remove,
|
|
.driver = {
|
|
.name = RGA_NAME,
|
|
.pm = &rga_pm,
|
|
.of_match_table = rockchip_rga_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(rga_pdrv);
|
|
|
|
MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
|
|
MODULE_DESCRIPTION("Rockchip Raster 2d Graphic Acceleration Unit");
|
|
MODULE_LICENSE("GPL");
|